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Alexandre M. Amory
- > Home > Persons > Alexandre M. Amory
Publications
- 2013
- [c25]Alexandre M. Amory, Matheus T. Moreira, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Cristiano Lazzari, Marcelo Soares Lubaszewski:
Evaluating the scalability of test buses. ISSoC 2013: 1-6 - [c24]Alexandre M. Amory, Edson I. Moreno, Fernando Moraes, Marcelo Lubaszewski:
Determining the test sources/sinks for NoC TAMs. ISVLSI 2013: 8-13 - 2011
- [j3]Alexandre M. Amory, Cristiano Lazzari, Marcelo Lubaszewski, Fernando Gehm Moraes:
A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms. J. Parallel Distributed Comput. 71(5): 675-686 (2011) - [c21]Alexandre M. Amory, Luciano Ost, César A. M. Marcon, Fernando Gehm Moraes, Marcelo Lubaszewski:
Evaluating energy consumption of homogeneous MPSoCs using spare tiles. DATE 2011: 1164-1167 - [c20]Alexandre M. Amory, César A. M. Marcon, Fernando Gehm Moraes, Marcelo Lubaszewski:
Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the energy consumption and the application execution time. International Symposium on Rapid System Prototyping 2011: 164-170 - [c19]Alexandre M. Amory, Cristiano Lazzari, Marcelo Lubaszewski, Fernando Gehm Moraes:
Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs. SBCCI 2011: 73-78 - 2008
- [j2]Érika F. Cota, Fernanda Gusmão de Lima Kastensmidt, Maico Cassel, Marcos Hervé, Pedro Almeida, Paulo Meirelles, Alexandre M. Amory, Marcelo Lubaszewski:
A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip. IEEE Trans. Computers 57(9): 1202-1215 (2008) - 2007
- [j1]Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes:
Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism. IET Comput. Digit. Tech. 1(3): 197-206 (2007) - [c16]Érika F. Cota, Fernanda Lima Kastensmidt, Maico Cassel, Paulo Meirelles, Alexandre M. Amory, Marcelo Lubaszewski:
Redefining and testing interconnect faults in Mesh NoCs. ITC 2007: 1-10 - [c15]Alexandre M. Amory, Frederico Ferlini, Marcelo Lubaszewski, Fernando Moraes:
DfT for the Reuse of Networks-on-Chip as Test Access Mechanism. VTS 2007: 435-440 - [i1]Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno:
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. CoRR abs/0710.4795 (2007) - 2006
- [c14]Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes:
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism. ETS 2006: 213-218 - 2005
- [c13]Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno:
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. DATE 2005: 62-63 - [c12]Alexandre M. Amory, Eduardo Wenzel Brião, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes:
A scalable test strategy for network-on-chip routers. ITC 2005: 9 - 2004
- [c11]Alexandre M. Amory, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes:
Reducing test time with processor reuse in network-on-chip based systems. SBCCI 2004: 111-116
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