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2010 – 2019
- 2017
[b1]Te-Hui Chen:
High-speed, low cost test platform using FPGA technology. Georgia Institute of Technology, Atlanta, GA, USA, 2017- 2016
- [j1]Nicholas Tzou, Debesh Bhatta, Xian Wang, Te-Hui Chen, Sen-Wen Hsiao, Barry J. Muldrey
, Hyun Woo Choi, Abhijit Chatterjee:
Concurrent Multi-Channel Crosstalk Jitter Characterization Using Coprime Period Channel Stimulus. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(6): 859-870 (2016) - [c5]Te-Hui Chen, David C. Keezer:
An Ultra-High-Speed Test Module and FPGA-Based Development Platform. ATS 2016: 269-274 - [c4]Te-Hui Chen, David C. Keezer:
A 40Gbps economic extension board and FPGA-based testing platform. ETS 2016: 1-2 - 2015
- [c3]David C. Keezer, Te-Hui Chen, Thomas Moon, D. T. Stonecypher, Abhijit Chatterjee, Hyun Woo Choi, Sungyeol Kim, Hosun Yoo:
An FPGA-based ATE extension module for low-cost multi-GHz memory test. ETS 2015: 1-6 - 2013
- [c2]David C. Keezer, Carl Edward Gray, Te-Hui Chen, Ashraf Majid:
Practical methods for extending ATE to 40 and 50Gbps. ITC 2013: 1-10 - 2012
- [c1]David C. Keezer, Te-Hui Chen, Carl Edward Gray, Hyun Woo Choi, Sungyeol Kim, Seongkwan Lee, Hosun Yoo:
Multi-gigahertz arbitrary timing generator and data pattern serializer/formatter. ITC 2012: 1-11
Coauthor Index
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