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ORCIDJean-Luc Béchennec
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2020 – today
- 2024
[c41]Hugo Reymond
, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Isabelle Puaut, Erven Rohou:
SCHEMATIC: Compile-Time Checkpoint Placement and Memory Allocation for Intermittent Systems. CGO 2024: 258-269- [c40]Hugo Reymond, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Isabelle Puaut, Erven Rohou:
EarlyBird: Energy belongs to those who wake up early. RTCSA 2024: 1-10 - 2023
- [j14]Antoine Bernabeu, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Olivier H. Roux:
Cost-optimal timed trace synthesis for scheduling of intermittent embedded systems. Discret. Event Dyn. Syst. 33(1): 63-93 (2023) - [j13]Imane Haur, Jean-Luc Béchennec, Olivier H. Roux:
Formal verification process of the compliance of a multicore AUTOSAR OS. Softw. Qual. J. 31(2): 497-531 (2023) - [c39]Sébastien Pillement, Maria Mendez Real, J. Pottier, T. Nieddu, Bertrand Le Gal, Sébastien Faucou, Jean-Luc Béchennec, Mikaël Briday, Sylvain Girbal, Jimmy Le Rhun, Olivier Gilles, Daniel Gracia Pérez, André Sintzoff, Jean-Roch Coulon:
Securing a RISC-V architecture: A dynamic approach. DATE 2023: 1-5 - 2022
- [c38]Imane Haur, Jean-Luc Béchennec, Olivier H. Roux:
High-level Colored Time Petri Nets for true concurrency modeling in real-time software. CoDIT 2022: 21-26 - [c37]Imane Haur, Jean-Luc Béchennec, Olivier H. Roux:
Formal Verification of the Inter-core Synchronization of a Multi-core RTOS Kernel. ICFEM 2022: 140-155 - 2021
- [j12]Jean-Luc Béchennec, Didier Lime, Olivier H. Roux:
Logical time control of concurrent DES. Discret. Event Dyn. Syst. 31(2): 185-217 (2021) - [c36]Vincent Lostanlen, Antoine Bernabeu, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Mathieu Lagrange:
Energy Efficiency is Not Enough: Towards a Batteryless Internet of Sounds. Audio Mostly Conference 2021: 147-155 - [c35]Imane Haur, Jean-Luc Béchennec, Olivier Henri Roux:
Formal schedulability analysis based on multi-core RTOS model. RTNS 2021: 216-225 - 2020
- [c34]Khaoula Boukir, Jean-Luc Béchennec, Anne-Marie Déplanche:
Requirement specification and model-checking of a real-time scheduler implementation. RTNS 2020: 89-99
2010 – 2019
- 2019
- [c33]Jean-Luc Béchennec, Didier Lime, Olivier H. Roux:
Control of DES with Urgency, Avoidability and Ineluctability. ACSD 2019: 92-101 - 2018
- [j11]Jean-Luc Béchennec, Sébastien Faucou, Olivier H. Roux, Matthias Brun, Louis-Marie Givel:
Testing Real-Time Systems With Runtime Enforcement. IEEE Des. Test 35(4): 31-37 (2018) - [c32]Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday:
HW-based Architecture for Runtime Verification of Embedded Software on SoPC systems. AHS 2018: 249-256 - [c31]Jean-Luc Béchennec, Olivier Henry Roux, Tigori Kabland Toussaint Gautier:
Formal model-based conformance verification of an OSEK/VDX compliant RTOS. CoDIT 2018: 628-634 - [c30]Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement:
Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection. EDCC 2018: 25-32 - [c29]Khaoula Boukir, Jean-Luc Béchennec, Anne-Marie Déplanche:
Formal approach for a verified implementation of Global EDF in Trampoline. RTNS 2018: 83-92 - 2017
- [j10]Tigori Kabland Toussaint Gautier, Jean-Luc Béchennec, Sébastien Faucou, Olivier Henry Roux:
Formal Model-Based Synthesis of Application-Specific Static RTOS. ACM Trans. Embed. Comput. Syst. 16(4): 97:1-97:25 (2017) - [c28]Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou:
WCET Analysis by Model Checking for a Processor with Dynamic Branch Prediction. VECoS 2017: 64-78 - 2016
- [c27]Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement:
Hardware runtime verification of embedded software in SoPC. SIES 2016: 171-176 - [c26]Louis-Marie Givel, Jean-Luc Béchennec, Matthias Brun, Sébastien Faucou, Olivier H. Roux:
Testing real-time embedded software using runtime enforcement. SIES 2016: 199-204 - [c25]Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou:
BEST: a Binary Executable Slicing Tool. WCET 2016: 7:1-7:10 - 2015
- [j9]Sylvain Cotard, Audrey Queudet, Jean-Luc Béchennec, Sébastien Faucou, Yvon Trinquet:
STM-HRT: A Robust and Wait-Free STM for Hard Real-Time Multicore Embedded Systems. ACM Trans. Embed. Comput. Syst. 14(4): 66:1-66:25 (2015) - [c24]Tigori Kabland Toussaint Gautier, Jean-Luc Béchennec, Olivier Henry Roux:
Formal Synthesis of Optimal RTOS. HPCC/CSS/ICESS 2015: 977-983 - 2014
- [c23]Julien Tanguy, Jean-Luc Béchennec, Mikaël Briday, Olivier H. Roux:
Reactive embedded device driver synthesis using logical timed models. SIMULTECH 2014: 163-169 - [c22]Adrien Bullich, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet:
Improving processor hardware compiled cycle accurate simulation using program abstraction. SimuTools 2014: 186-194 - 2013
- [c21]Franck Cassez, Jean-Luc Béchennec:
Timing Analysis of Binary Programs with UPPAAL. ACSD 2013: 41-50 - [c20]Julien Tanguy, Jean-Luc Béchennec, Mikaël Briday, Sebastien Dube, Olivier H. Roux:
Device driver synthesis for embedded systems. ETFA 2013: 1-8 - 2012
- [j8]Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Guillaume Savaton, Yvon Trinquet:
Harmless, a hardware architecture description language dedicated to real-time embedded system simulation. J. Syst. Archit. 58(8): 318-337 (2012) - [c19]Sylvain Cotard, Sébastien Faucou, Jean-Luc Béchennec, Audrey Queudet, Yvon Trinquet:
A Data Flow Monitoring Service Based on Runtime Verification for AUTOSAR. HPCC-ICESS 2012: 1508-1515 - 2011
- [j7]Guillaume Savaton, Jean-Luc Béchennec, Mikaël Briday, Rola Kassem:
An Architecture Description Language for Embedded Hardware Platforms. Electron. Commun. Eur. Assoc. Softw. Sci. Technol. 44 (2011) - [c18]Jean-Luc Béchennec, Mikaël Briday, Valere Alibert:
Extending Harmless architecture description language for embedded real-time systems validation. SIES 2011: 223-231 - [i1]Jean-Luc Béchennec, Franck Cassez:
Computation of WCET using Program Slicing and Real-Time Model-Checking. CoRR abs/1105.1633 (2011) - 2010
- [c17]Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Florent Pavin, Fabien Juif:
ViPER: a lightweight approach to the simulation of distributed and embedded software. SimuTools 2010: 74
2000 – 2009
- 2009
- [c16]Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet, Guillaume Savaton:
Instruction set simulator generation using HARMLESS, a new hardware architecture description language. SimuTools 2009: 24 - 2008
- [c15]Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet, Guillaume Savaton:
Simulator generation using an automaton based pipeline model for timing analysis. IMCSIT 2008: 657-664 - 2006
- [c14]Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Yvon Trinquet:
Trampoline An Open Source Implementation of the OSEK/VDX RTOS Specification. ETFA 2006: 62-69 - 2002
- [j6]Nathalie Drach, Jean-Luc Béchennec, Olivier Temam:
Increasing hardware data prefetching performance using the second-level cache. J. Syst. Archit. 48(4-5): 137-149 (2002) - 2000
- [c13]Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam:
The Best Distribution for a Parallel OpenGL 3D Engine with Texture Caches. HPCA 2000: 399-408
1990 – 1999
- 1999
- [c12]Claude Limousin, Alexis Vartanian, Jean-Luc Béchennec:
PopSPY: A PowerPC Instrumentation Tool for Multiprocessor Simulation. Euro-Par 1999: 262-265 - [c11]Julien Sébot, Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam:
A Parallel Algorithm for 3D Geometry Transformations in OpenGL. Euro-Par 1999: 659-662 - [c10]Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam:
Two Schemes to Improve the Performance of a Sort-Last 3D Parallel Rendering Machine with Texture Caches. Euro-Par 1999: 757-760 - 1998
- [c9]Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam:
Evaluation of High Performance Multicache Parallel Texture Mapping. International Conference on Supercomputing 1998: 289-296 - [c8]Jean-Luc Béchennec:
ASF: a teaching and rsearch object-oriented simulation tool for computer architecture design and performance evaluation. WCAE@ISCA 1998: 18 - 1997
- [c7]A. Pavlov, Jean-Luc Béchennec, Daniel Etiemble:
Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces. EUROMICRO 1997: 409- - 1993
- [j5]Cécile Germain, Jean-Luc Béchennec, Daniel Etiemble, Jean-Paul Sansonnet:
A Communication Architecture for a Massively Parallel Message-Passing Multicomputer. J. Parallel Distributed Comput. 19(4): 338-348 (1993) - [j4]Vincent Néri, Jean-Luc Béchennec, Franck Cappello, Daniel Etiemble:
Hardware features of the static communication network of a parallel architecture. Microprocess. Microprogramming 38(1-5): 19-24 (1993) - [c6]Franck Cappello, Jean-Luc Béchennec, Franck Delaplace, Cécile Germain, Jean-Louis Giavitto, Vincent Néri, Daniel Etiemble:
Balanced Distributed Memory Parallel Computers. ICPP (1) 1993: 72-76 - [c5]Franck Cappello, Jean-Luc Béchennec, Franck Delaplace, Damien Gautier de Lahaut, Cécile Germain, Jean-Louis Giavitto, Vincent Néri, Daniel Etiemble:
A Parralel Architecture Based on Compiled Communication Schemes. PARCO 1993: 371-378 - [c4]E. Daugeras, Jean-Luc Béchennec, Franck Cappello:
Static computation of standard linear algebra subroutines for PTAH. PDP 1993: 30-34 - 1992
- [j3]Franck Cappello, Jean-Luc Béchennec, J.-L. Glavitto:
Design of the processing node of the PTAH 64 parallel computer. Microprocess. Microprogramming 35(1-5): 105-111 (1992) - [c3]Franck Cappello, Jean-Luc Béchennec, Jean-Louis Giavitto:
PTAH: Introduction to a New Parallel Architecture for Highly Numeric Processing. PARLE 1992: 81-96 - 1991
- [j2]Jean-Luc Béchennec, Franck Cappello, Daniel Etiemble:
3D hardware packages for parallel architectures. Microprocessing and Microprogramming 32(1-5): 171-177 (1991) - 1990
- [j1]Franck Cappello, Jean-Luc Béchennec, Daniel Etiemble:
A risc central processing unit for a massivelly parallel architecture. Microprocessing and Microprogramming 30(1-5): 33-39 (1990)
1980 – 1989
- 1988
- [c2]Pascal Faudemay, Daniel Etiemble, Jean-Luc Béchennec:
A highly parallel processor with an instruction set including relational algebra. ICCD 1988: 537-538 - 1987
- [c1]Pascal Faudemay, Daniel Etiemble, Jean-Luc Béchennec, He Hé:
The Database Processor 'RAPID'. IWDM 1987: 171-187
Coauthor Index
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