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ORCIDIntegration, Volume 52
Volume 52, January 2016
- Jin Sun, Liang Xiao, Jiangshan Tian, He Zhou
, Janet Roveda:
Surrogating circuit design solutions with robustness metrics. 1-9 - Kai He, Sheldon X.-D. Tan, Hengyang Zhao, Xuexin Liu, Hai Wang, Guoyong Shi:
Parallel GMRES solver for fast analysis of large linear dynamic systems on GPU platforms. 10-22 - Xiaokun Yang, Nansong Wu, Jean H. Andrian:
A novel bus transfer mode (AS transfer) and a performance evaluation methodology. 23-33 - P. Balasubramanian:
Comments on "Dual-rail asynchronous logic multi-level implementation". 34-40 - Jun Zhou, Huawei Li, Tiancheng Wang, Xiaowei Li:
LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs. 41-50 - Esmaeil Fatemi-Behbahani, Ebrahim Farshidi, Karim Ansari-Asl:
A new approach to analysis of residue probability density function in pipelined ADCs. 51-61 - Aroutchelvame Mayilavelane, Brian Berscheid:
A Fast FIR filtering technique for multirate filters. 62-70 - Giray Kömürcü, Ali Emre Pusane, Günhan Dündar:
Effects of aging and compensation mechanisms in ordering based RO-PUFs. 71-76 - Zhiting Yan, Guanghui He, Weifeng He, Shuaijie Wang, Zhigang Mao:
High performance parallel turbo decoder with configurable interleaving network for LTE application. 77-90 - Juyeon Kim, Deokjin Joo, Taewhan Kim:
Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes. 91-101
- Alessandro Cilardo, Edoardo Fusella:
Design automation for application-specific on-chip interconnects: A survey. 102-121
- Pedro Mendonça dos Santos, Luís Mendes, João Caldinhas Vaz:
Substrate noise isolation improvement in a single-well standard CMOS process. 122-128 - Mahshid Nasserian, Mohammad Kafi Kangi, Mohammad Maymandi-Nejad, Farshad Moradi:
A low-power fast tag comparator by modifying charging scheme of wide fan-in dynamic OR gates. 129-141 - Yin Li, Yi-yang Chen:
New bit-parallel Montgomery multiplier for trinomials using squaring operation. 142-155 - Pilin Junsangsri, Jie Han, Fabrizio Lombardi:
Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction. 156-167 - Yishai Statter, Tom Chen:
A novel high-throughput method for table look-up based analog design automation. 168-181
- Elisenda Roca, Javier J. Sieiro:
Introduction to the special issue on Radio Frequency Integrated Circuits (RFIC) design techniques. 183-184 - Renzhi Liu, Lawrence T. Pileggi, Jeffrey A. Weldon:
A wideband RF receiver with extended statistical element selection based harmonic rejection calibration. 185-194 - Salma Elabd, Waleed Khalil:
Impact of technology scaling on the tuning range and phase noise of mm-wave CMOS LC-VCOs. 195-207 - David del Rio, Iñaki Gurutzeaga, Héctor Solar, Andoni Beriain, Roc Berenguer:
Layout-aware design methodology for a 75 GHz power amplifier in a 55 nm SiGe technology. 208-216 - Farshad Eshghabadi, Fatemeh Banitorfian, Norlaili Mohd Noh, Mohd Tafir Mustaffa, Asrulnizam Bin Abd Manaf:
Post-process die-level electromagnetic field analysis on microwave CMOS low-noise amplifier for first-pass silicon fabrication success. 217-227 - Rafaella Fiorelli, Eduardo J. Peralías:
Semi-empirical RF MOST model for CMOS 65 nm technologies: Theory, extraction method and validation. 228-236 - Amin Sallem, Pedro Pereira, M. Helena Fino, Mourad Fakhfakh:
A hybrid approach for the sensitivity analysis of integrated inductors. 237-242 - Ricardo Povoa, Ivan Bastos, Nuno Lourenço, Nuno Horta:
Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques. 243-252 - Hojat Ghonoodi, Hossein Miar Naimi, Mohammad Gholami:
Analysis of frequency and amplitude in CMOS differential ring oscillators. 253-259 - João Casaleiro, Luís B. Oliveira, Igor M. Filanovsky:
A quadrature RC-oscillator with capacitive coupling. 260-271 - Jorge Alves Torres, João Costa Freire:
K Band SiGe HBT single ended active inductors. 272-281 - Atefeh Salimi, Rasoul Dehghani, Abdolreza Nabavi:
A digital predistortion assisted hybrid supply modulator for envelope tracking power amplifiers. 282-290 - José-Cruz Nuñez Pérez, José Ricardo Cárdenas-Valdez, Katherine Montoya-Villegas, J. Apolinar Reynoso-Hernández, José Raúl Loo-Yau, Christian Gontrand, Esteban Tlelo-Cuautle:
FPGA-based test bed for measurement of AM/AM and AM/PM distortion and modeling memory effects in RF PAs. 291-300 - Alireza Saberkari, Saman Ziabakhsh, Herminio Martínez, Eduard Alarcón:
Active inductor-based tunable impedance matching network for RF power amplifier application. 301-308 - Ivan Bastos, Luís Bica Oliveira, João Goes, João Pedro Oliveira, Manuel Medeiros Silva:
Noise canceling LNA with gain enhancement by using double feedback. 309-315 - Atiyeh Karimlou, Roya Jafarnejad, Jafar Sobhi:
An Inductor-less Sub-mW Low Noise Amplifier for Wireless Sensor Network Applications. 316-322 - Alireza Saberkari, Shima Kazemi, Vahideh Shirmohammadli, Mustapha C. E. Yagoub:
gm-boosted flat gain UWB low noise amplifier with active inductor-based input matching network. 323-333
- Rabab Ezz-Eldin, Magdy A. El-Moursy, Hesham F. A. Hamed:
Corrigendum to "High throughput asynchronous NoC design under high process variation" [Integr. VLSI J. (2015) 1-13]. 334
- Zhufei Chu, Yinshui Xia, Lun-Yao Wang:
Multi-supply voltage (MSV) driven SoC floorplanning for fast design convergence. 335-346 - Tiago Reimann, Cliff C. N. Sze, Ricardo Reis:
Challenges of cell selection algorithms in industrial high performance microprocessor designs. 347-354 - Julia Funke, Stefan Hougardy, Jan Schneider:
An exact algorithm for wirelength optimal placements in VLSI design. 355-366 - Syed Rafay Hasan, Waqas Gul, Osman Hasan:
Clock domain crossing (CDC) in 3D-SICs: Semi QDI asynchronous vs loosely synchronous. 367-380
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