default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIBM Journal of Research and Development, Volume 28, 1984
Please be aware that the table of contents given here is incomplete.
Volume 28, Number 1, January 1984
- Edward N. Adams:
Optimizing Preventive Service of Software Products. 2-14 - Nancy R. Hall, Stanley Preiser:
Combined Network Complexity Measures. 15-27 - John F. Sowa:
Interactive Language Implementation System. 28-39 - Frederic N. Ris:
Experience with Access Functions in an Experimental Compiler. 40-51 - Robert Strom, Nagui Halim:
A New Programming Methodology for Long-Lived Software Systems. 52-59 - Cyril N. Alberga, Allen L. Brown, George B. Leeman Jr., Martin Mikelsons, Mark N. Wegman:
A Program Development Tool. 60-73 - Vincent J. Kruskal:
Managing Multi-Version Programs with an Editor. 74-81 - Marco A. Casanova, Jose E. Amaral de Sa:
Mapping Uninterpreted Schemes into Entity-Relationship Diagrams: Two Applications to Conceptual Schema Design. 82-94 - Ambuj Goyal, Tilak Agerwala:
Performance Analysis of Future Shared Storage Systems. 95-108
Volume 28, Number 2, March 1984
- Chin-Long Chen, M. Y. (Ben) Hsiao:
Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review. 124-134 - Glen G. Langdon Jr.:
An Introduction to Arithmetic Coding. 135-149 - Richard E. Blahut:
A Universal Reed-Solomon Decoder. 150-158 - Jean Arlat, William C. Carter:
Implementation and Evaluation of a (b, k)-Adjacent Error-Correcting/Detecting Scheme for Supercomputer Systems. 159-169 - Douglas C. Bossen, Chin-Long Chen, M. Y. (Ben) Hsiao:
Fault Alignment Exclusion for Memory Using Address Permutation. 170-176 - F. J. Aichelmann Jr.:
Fault-Tolerant Design Techniques for Semiconductor Memory Applications. 177-183 - C. L. Chen, Robert A. Rutledge:
Fault-Tolerant Memory Simulator. 184-195 - Marvin R. Libson, Harold E. Harvey:
A General-Purpose Memory Reliability Simulator. 196-205 - Thomas D. Howell:
Analysis of Correctable Errors in the IBM 3380 Disk File. 206-211 - Donald T. Tang, C. L. Chen:
Iterative Exhaustive Pattern Generation for Logic Testing. 212-219
Volume 28, Number 4, July 1984
- David R. Tryon, Fred M. Armstrong, Mark R. Reiter:
Statistical Failure Analysis of System Timing. 340-355 - Michael J. Flynn, Lee W. Hoevel:
Measures of Ideal Execution Architectures. 356-369 - Anthony Correale:
Design Considerations of a Static LSSD Polarity Hold Latch Pair. 370-378 - Richard E. Matick, Daniel T. Ling, Satish Gupta, Frederick Dill:
All Points Addressable Raster Display Memory. 379-392 - Daniel L. Ostapko:
A Mapping and Memory Chip Hardware which Provides Symmetric Reading/Writing of Horizontal and Vertical Lines. 393-398 - Jitendra V. Dave, Jenö Gazdag:
Reduction of Random Noise from Multiband Image Data Using Phase Relationships Among Their Fourier Coefficients. 399-411 - Donald L. Orth:
Empty Arrays in Extended APL. 412-427 - Mitsuru Ohba:
Software Reliability Analysis Models. 428-443 - Emil Hopner, Michael Allen Patten:
The Digital Data Exchange - A Space-Division Switching System. 444-453 - Sherri J. Gillespie:
Resist Profile Control in E-Beam Lithography. 454-460 - Charles H. Stapper:
Modeling of Defects in Integrated Circuit Photolithographic Patterns. 461-475 - Michael Held, Alan J. Hoffman, Ellis Lane Johnson, Philip Wolfe:
Aspects of the Traveling Salesman Problem. 476-486
Volume 28, Number 5, September 1984
- Richard L. Taylor:
A Software Architecture for a Mature Design Automation System. 501-512 - Ronald B. Capelli, George C. Sax:
A Device-Independent Graphics Package for CAD Applications. 512-523 - Walter H. Elder, Peter P. Zenewicz, Rita R. Alvarodiaz:
An Interactive System for VLSI Chip Physical Design. 524-537 - John A. Darringer, Daniel Brand, John V. Gerbi, William H. Joyner Jr., Louise Trevillyan:
LSS: A System for Production Logic Synthesis. 537-545 - James L. Gilkinson, Steven D. Lewis, Bruce B. Winter, Amir Hekmatpour:
Automated Technology Mapping. 546-556 - Leon I. Maissel, Hillel Ofek:
Hardware Design and Description Languages in IBM. 557-563 - Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Gabriel M. Silberman:
Using a Hardware Simulation Engine for Custom MOS Structured Designs. 564-571 - Rolf-Dieter Fiebrich, Yuh-Zen Liao, George M. Koppelman, Edward N. Adams:
PSI: A Symbolic Layout System. 572-580 - Peter W. Cook:
Constraint Solver for Generalized IC Layout. 581-589 - A. M. Barone, J. K. Morrell:
Custom Chip/Card Design System. 590-595 - Peter S. Hauge, Ellen J. Yoffa:
ACORN: A System for CVS Macro Design by Tree Placement and Tree Customization. 596-602 - Peter C. Elmendorf:
KWIRE: A Multiple-Technology, User-Reconfigurable Wiring Tool for VLSI. 603-612 - Ralph Linsker:
An Iterative-Improvement Penalty-Function-Driven Wire Routing System. 613-624 - D. Leet, P. Shearon, R. France:
A CMOS LSSD Test Generation System. 625-635 - Charles H. Stapper:
Yield Model for Fault Clusters Within Integrated Circuits. 636-640
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-07-25 19:05 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
