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ORCID24th COOL CHIPS 2021: Tokyo, Japan
- IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021, Tokyo, Japan, April 14-16, 2021. IEEE 2021, ISBN 978-1-6654-1503-3
- Takaki Urabe, Hiroyuki Ochi, Kazutoshi Kobayashi:
Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-Standby and Instant-Powerup Embedded Memory on IoT. 1-3 - Eishi Arima, Yuetsu Kodama, Tetsuya Odajima, Miwako Tsuji
, Mitsuhisa Sato:
Power/Performance/Area Evaluations for Next-Generation HPC Processors using the A64FX Chip. 1-6 - Shunsuke Tsukada, Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi:
A Metadata Prefetching Mechanism for Hybrid Memory Architectures. 1-3 - Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano:
Hybrid Network of Packet Switching and STDM in a Multi-FPGA System. 1-6 - Sugahara Takuya, Renyuan Zhang, Yasuhiko Nakashima:
Training Low-Latency Spiking Neural Network through Knowledge Distillation. 1-3 - Donghyeon Han, Dongseok Im, Gwangtae Park, Youngwoo Kim, Seokchan Song, Juhyoung Lee, Hoi-Jun Yoo:
An Energy-Efficient Deep Neural Network Training Processor with Bit-Slice-Level Reconfigurability and Sparsity Exploitation. 1-3 - Ayan Datta, Karanvir Singh, Arpita Dutta, Kousik Debnath:
A Timing Aware Connectivity Optimization Technique for Improving Energy Efficiency of High-Performance CPUs. 1-6 - Zhenshan Bao, Kang Zhan, Wenbo Zhang, Junnan Guo:
LSFQ: A Low Precision Full Integer Quantization for High-Performance FPGA-Based CNN Acceleration. 1-6 - Van Dai Phan, Hoai Luan Pham, Thi Hong Tran, Yasuhiko Nakashima:
High Performance Multicore SHA-256 Accelerator using Fully Parallel Computation and Local Memory. 1-3 - Stanislav Sedukhin, Yoichi Tomioka, Kohei Yamamoto:
In Search of the Performance- and Energy-Efficient CNN Accelerators. 1-6
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