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Hoai Luan Pham

Hoai-Luan Pham – Pham Hoai Luan

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affiliation: Nara Institute of Science and Technology, NAIST, Graduate School of Information Science, Japan

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2020 – today

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2024
[j9]
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Vu Trung Duong Le, Hoai-Luan Pham, Thi Hong Tran, Yasuhiko Nakashima:
Flexible and Energy-Efficient Crypto-Processor for Arbitrary Input Length Processing in Blockchain-Based IoT Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(3): 319-330 (2024)
[c17]
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  - conf/coolchips/LuanNLTVTN24
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Pham Hoai Luan, Hai Hau Nguyen, Vu Trung Duong Le, Thi Diem Tran, Tuan Hai Vu, Thi Hong Tran, Yasuhiko Nakashima:
MRCA: Multi-grained Reconfigurable Cryptographic Accelerator for Diverse Security Requirements. COOL CHIPS 2024: 1-6
2023
[j8]
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Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
Flexible and Scalable BLAKE/BLAKE2 Coprocessor for Blockchain-Based IoT Applications. IEEE Des. Test 40(5): 15-25 (2023)
[j7]
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  - journals/sensors/LamDP23
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Duc Khai Lam, Cam Vinh Du, Hoai Luan Pham:
QuantLaneNet: A 640-FPS and 34-GOPS/W FPGA-Based CNN Accelerator for Lane Detection. Sensors 23(15): 6661 (2023)
[c16]
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  - conf/candar/LePTDN23
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Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Thi Sang Duong, Yasuhiko Nakashima:
Efficient and High-Speed CGRA Accelerator for Cryptographic Applications. candar 2023: 189-195
[c15]
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  - conf/icicdt/LePTNDN23
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Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Quoc Duy Nam Nguyen, Thi Sang Duong, Yasuhiko Nakashima:
Versatile Resource-shared Cryptographic Accelerator for Multi-Domain Applications. ICICDT 2023: 104-107
[c14]
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Vu Trung Duong Le, Hoai Luan Pham, Thi Sang Duong, Thi Hong Tran, Quoc Duy Nam Nguyen, Yasuhiko Nakashima:
RHCP: A Reconfigurable High-efficient Cryptographic Processor for Decentralized IoT Platforms. KSE 2023: 1-6
[c13]
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Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Thi Diem Tran, Ren Imamura, Quoc Duy Nam Nguyen, Thi Hong Tran, Yasuhiko Nakashima:
Universal 32/64-bit CGRA for Lightweight Cryptography in Securing IoT Data Transmission. MCSoC 2023: 419-425
[c12]
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Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Thi Sang Duong, Yasuhiko Nakashima:
High-efficiency Reconfigurable Crypto Accelerator Utilizing Innovative Resource Sharing and Parallel Processing. MCSoC 2023: 576-583
[c11]
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  - conf/mwscas/LuanDLTN23
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Pham Hoai Luan, Thi Sang Duong, Vu Trung Duong Le, Thi Hong Tran, Yasuhiko Nakashima:
Energy-Efficient Unified Multi-Hash Coprocessor for Securing IoT Systems Integrating Blockchain. MWSCAS 2023: 355-359
[c10]
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  - conf/rivf/DuongPLITN23
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Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Ren Imamura, Thi Hong Tran, Yasuhiko Nakashima:
Small-Footprint Reconfigurable Heterogeneous Cryptographic Accelerator for Fog Computing. RIVF 2023: 124-129
[c9]
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Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Thi Hong Tran, Yasuhiko Nakashima:
Power-Efficient and Programmable Hashing Accelerator for Massive Message Processing. SOCC 2023: 1-6
2022
[j6]
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Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
A High-Efficiency FPGA-Based Multimode SHA-2 Accelerator. IEEE Access 10: 11830-11845 (2022)
[j5]
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Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
Compact Message Permutation for a Fully Pipelined BLAKE-256/512 Accelerator. IEEE Access 10: 68740-68754 (2022)
[c8]
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Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
A Coarse Grained Reconfigurable Architecture for SHA-2 Acceleration. IPDPS Workshops 2022: 671-678
[c7]
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  - conf/mwscas/LuanaTLN22
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Pham Hoai Luan, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
A High-Efficiency FPGA-based BLAKE-256 Accelerator for Securing Blockchain Networks. MWSCAS 2022: 1-4
[c6]
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  - conf/sbcci/LeLTN22
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Vu Trung Duong Le, Pham Hoai Luan, Thi Hong Tran, Yasuhiko Nakashima:
CSIP: A Compact Scrypt IP design with single PBKDF2 core for Blockchain mining. SBCCI 2022: 1-6
[c5]
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Pham Hoai Luan, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
A Flexible and Energy-Efficient BLAKE-256/2s Co-Processor for Blockchain-based IoT Applications. SBCCI 2022: 1-6
2021
[j4]
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  - journals/access/TranPN21
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Thi Hong Tran, Hoai Luan Pham, Yasuhiko Nakashima:
A High-Performance Multimem SHA-256 Accelerator for Society 5.0. IEEE Access 9: 39182-39192 (2021)
[j3]
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Vu Trung Duong Le, Thi Hong Tran, Hoai Luan Pham, Duc Khai Lam, Yasuhiko Nakashima:
MRSA: A High-Efficiency Multi ROMix Scrypt Accelerator for Cryptocurrency Mining and Data Security. IEEE Access 9: 168383-168396 (2021)
[j2]
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  - journals/tcasI/TranPPN21
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Thi Hong Tran, Hoai Luan Pham, Tri Dung Phan, Yasuhiko Nakashima:
BCA: A 530-mW Multicore Blockchain Accelerator for Power-Constrained Devices in Securing Decentralized Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 68(10): 4245-4258 (2021)
[c4]
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  - conf/coolchips/PhanPTN21
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Van Dai Phan, Hoai Luan Pham, Thi Hong Tran, Yasuhiko Nakashima:
High Performance Multicore SHA-256 Accelerator using Fully Parallel Computation and Local Memory. COOL CHIPS 2021: 1-3
2020
[j1]
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  - journals/access/PhamTPDLN20
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Hoai Luan Pham, Thi Hong Tran, Tri Dung Phan, Vu Trung Duong Le, Duc Khai Lam, Yasuhiko Nakashima:
Double SHA-256 Hardware Architecture With Compact Message Expander for Bitcoin Mining. IEEE Access 8: 139634-139646 (2020)

2010 – 2019

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2019
[c3]
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  - conf/icbc2/NguyenPTHN19
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Van-Cam Nguyen, Hoai-Luan Pham, Thi Hong Tran, Huu-Thuan Huynh, Yasuhiko Nakashima:
Digitizing Invoice and Managing VAT Payment Using Blockchain Smart Contract. IEEE ICBC 2019: 74-77
2018
[c2]
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  - conf/globecom/PhamTN18
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Hoai Luan Pham, Thi Hong Tran, Yasuhiko Nakashima:
A Secure Remote Healthcare System for Hospital Using Blockchain Smart Contract. GLOBECOM Workshops 2018: 1-6
[c1]
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  - conf/ispacs/LuanDLNO18
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Pham Hoai Luan, Nguyen Xuan Duc, Duc Khai Lam, Yuhei Nagao, Hiroshi Ochi:
Design and Hardware Implementation of Improved Precision Time Protocol for High Speed Automotive Wireless Transmission System. ISPACS 2018: 48-53

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