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ORCIDMicroprocessors and Microsystems, Volume 40
Volume 40, February 2016
- Bruno Cardoso Lopes, Leonardo Luiz Ecco, E. C. Xavier, Rodolfo Jardim de Azevedo
:
Design and evaluation of compact ISA extensions. 1-15 - Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, Habib Mehrez:
Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires. 16-26 - An Hsia, Ching-Wen Chen, Tzong-Jye Liu:
Energy-efficient synonym data detection and consistency for virtual cache. 27-44 - Fayez Gebali, Atef Ibrahim:
Low space-complexity and low power semi-systolic multiplier architectures over GF(2m) based on irreducible trinomial. 45-52 - John V. Vourvoulakis, John A. Kalomiros, John N. Lygouras:
Fully pipelined FPGA-based architecture for real-time SIFT extraction. 53-73 - Ujjwal Gupta, Spurthi Korrapati, Navyasree Matturu, Ümit Y. Ogras:
A generic energy optimization framework for heterogeneous platforms using scaling models. 74-87 - Ying Zhang, Samuel Irving, Lu Peng, Xin Fu, David M. Koppelman, Weihua Zhang, Jesse Ardonne:
Design space exploration for device and architectural heterogeneity in chip-multiprocessors. 88-101 - Peter Raab, Stefan Krämer, Jürgen Mottok:
Reliability of data processing and fault compensation in unreliable arithmetic processors. 102-112 - Muhammad Yasir Qadri, Nadia N. Qadri, Klaus D. McDonald-Maier:
Fuzzy logic based energy and throughput aware design space exploration for MPSoCs. 113-123 - Rourab Paul, Amlan Chakrabarti, Ranjan Ghosh:
Multi core SSL/TLS security processor architecture and its FPGA prototype design with automated preferential algorithm. 124-136 - Jarbas Silveira, César A. M. Marcon, Paulo Cortez, Giovanni Cordeiro Barroso, Joao Marcelo Ferreira, Rafael Mota:
Scenario preprocessing approach for the reconfiguration of fault-tolerant NoC-based MPSoCs. 137-153 - Ran Manevich, Israel Cidon, Avinoam Kolodny:
Design and dynamic management of hierarchical NoCs. 154-166 - Mark Hamilton, William P. Marnane:
Implementation of a secure TLS coprocessor on an FPGA. 167-180 - Pallab Kumar Nath, Swapna Banerjee:
A high speed, memory efficient line based VLSI architecture for the dual mode inverse discrete wavelet transform of JPEG2000 decoder. 181-188
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