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2020 – today
- 2020
[j6]Nimisha Ghosh, Rourab Paul, Satyabrata Maity, Krishanu Maity, Sayantan Saha:
Fault Matters: Sensor data fusion for detection of faults using Dempster-Shafer theory of evidence in IoT-based applications. Expert Syst. Appl. 162: 113887 (2020)- [i14]Nimisha Ghosh, Sayantan Saha, Rourab Paul:
iDCR: Improved Dempster Combination Rule for Multisensor Fault Diagnosis. CoRR abs/2002.03639 (2020) - [i13]Rourab Paul, Nimisha Ghosh, Amlan Chakrabarti, Prasant Mahapatra:
The Blockchain Based Auditor on Secret key Life Cycle in Reconfigurable Platform. CoRR abs/2007.06201 (2020)
2010 – 2019
- 2019
- [i12]Nimisha Ghosh, Rourab Paul, Satyabrata Maity, Krishanu Maity, Sayantan Saha:
Fault Matters: Sensor Data Fusion for Detection of Faults using Dempster-Shafer Theory of Evidence in IoT-Based Applications. CoRR abs/1906.09769 (2019) - [i11]Rourab Paul, Nimisha Ghosh, Suman Sau, Amlan Chakrabarti, Prasant Mahapatra:
IoT based Smart Access Controlled Secure Smart City Architecture Using Blockchain. CoRR abs/1908.11538 (2019) - 2018
- [j5]Rourab Paul, Gitesh Sikder, Amlan Chakrabarti
, Ranjan Ghosh:
Hardware variant NSP with security-aware automated preferential algorithm. IET Comput. Digit. Tech. 12(5): 192-205 (2018) - [j4]Rourab Paul, Sandeep K. Shukla:
Partitioned security processor architecture on FPGA platform. IET Comput. Digit. Tech. 12(5): 216-226 (2018) - 2017
- [j3]Swagata Mandal, Rourab Paul, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay:
Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware. Microprocess. Microsystems 51: 313-330 (2017) - [c4]Rourab Paul, Sandeep Kumar Shukla:
A High Speed KECCAK Coprocessor for Partitioned NSP Architecture on FPGA Platform. VDAT 2017: 507-518 - 2016
- [j2]Swagata Mandal, Rourab Paul, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay:
A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code. IEEE Embed. Syst. Lett. 8(4): 65-68 (2016) - [j1]Rourab Paul, Amlan Chakrabarti, Ranjan Ghosh:
Multi core SSL/TLS security processor architecture and its FPGA prototype design with automated preferential algorithm. Microprocess. Microsystems 40: 124-136 (2016) - [c3]Jubin Mitra, Shuaib Ahmad Khan, Rourab Paul, Sanjoy Mukherjee, Amlan Chakrabarti, Tapan Kumar Nayak:
Error Resilient Secure Multi-gigabit Optical Link Design for High Energy Physics Experiment. VLSI Design 2016: 427-432 - [i10]Rourab Paul, Hemanta Dey, Amlan Chakrabarti, Ranjan Ghosh:
Accelerating More Secure RC4 : Implementation of Seven FPGA Designs in Stages upto 8 byte per clock. CoRR abs/1609.01389 (2016) - 2015
- [c2]Saheli Ghosh, Subha Jyoti Das, Rourab Paul, Amlan Chakrabarti:
Multicore encryption and authentication on a reconfigurable hardware. ReTIS 2015: 173-177 - [i9]Swagata Mandal, Rourab Paul, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay:
A Novel Method for Soft Error Mitigation in FPGA using Adaptive Cross Parity Code. CoRR abs/1509.06891 (2015) - 2014
- [i8]Rourab Paul, Amlan Chakrabarti, Ranjan Ghosh:
Hardware Implementation of four byte per clock RC4 algorithm. CoRR abs/1401.2727 (2014) - [i7]Rourab Paul, Amlan Chakrabarti, Ranjan Ghosh:
Fault Detection for RC4 Algorithm and its Implementation on FPGA Platform. CoRR abs/1401.2732 (2014) - [i6]Sruti Agarwal, Sangeet Saha, Rourab Paul, Amlan Chakrabarti:
Performance Evaluation of ECC in Single and Multi Processor Architectures on FPGA Based Embedded System. CoRR abs/1401.3421 (2014) - [i5]Rourab Paul, Amlan Chakrabarti, Ranjan Ghosh:
Multi Core SSL/TLS Security Processor Architecture Prototype Design with automated Preferential Algorithm in FPGA. CoRR abs/1410.7560 (2014) - 2012
- [c1]Suman Sau, Rourab Paul, Tanmay Biswas, Amlan Chakrabarti:
A novel AES-256 implementation on FPGA using co-processor based architecture. ICACCI 2012: 632-638 - [i4]Rourab Paul, Sangeet Saha, J. K. M. Sadique Uz Zaman, Suman Das, Amlan Chakrabarti, Ranjan Ghosh:
A simple 1-byte 1-clock RC4 design and its efficient implementation in FPGA coprocessor for secured ethernet communication. CoRR abs/1205.1737 (2012) - [i3]Rourab Paul, Sangeet Saha, Suman Sau, Amlan Chakrabarti:
Design and implementation of real time AES-128 on real time operating system for multiple FPGA communication. CoRR abs/1205.2153 (2012) - [i2]Rourab Paul, Suman Sau, Amlan Chakrabarti:
Architecture for real time continuous sorting on large width data volume for fpga based applications. CoRR abs/1206.1567 (2012) - [i1]Sangeet Saha, Chandrajit Pal, Rourab Paul, Satyabrata Maity, Suman Sau:
A brief experience on journey through hardware developments for image processing and its applications on Cryptography. CoRR abs/1212.6303 (2012)
Coauthor Index
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