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Publication search results
found 21 matches
- 2007
- Messaoud Ahmed Ouameur, Daniel Massicotte:
Real-time DSP and FPGA Implementation of Wiener LMS Based Multipath Channel Estimation in 3G CDMA Systems. J. VLSI Signal Process. 47(3): 259-279 (2007) - Jeffrey M. Arnold:
The Architecture and Development Flow of the S5 Software Configurable Processor. J. VLSI Signal Process. 47(1): 3-14 (2007) - Gordon J. Brebner, Samarjit Chakraborty, Weng-Fai Wong:
Editorial for the Special Issue on Field Programmable Technology. J. VLSI Signal Process. 47(1): 1-2 (2007) - Albert Mo Kim Cheng, Feng Shang:
Priority-driven Coding and Transmission of Progressive JPEG Images for Real-Time Applications. J. VLSI Signal Process. 47(2): 169-182 (2007) - Albert M. K. Cheng, Zhubin Zhang:
Improving Web Server Performance with Adaptive Proxy Caching in Soft Real-time Mobile Applications. J. VLSI Signal Process. 47(2): 103-115 (2007) - José Gabriel F. Coutinho, M. P. T. Juvonen, J. L. Wang, Benny Lo, Wayne Luk, Oskar Mencer, Guang-Zhong Yang:
Designing a Posture Analysis System with Hardware Implementation. J. VLSI Signal Process. 47(1): 33-45 (2007) - Wei Han, Kwok-Wai Hon, Cheong-Fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun:
A Speech Recognition IC Using Hidden Markov Models with Continuous Observation Densities. J. VLSI Signal Process. 47(3): 223-232 (2007) - H. Jeong, Y. Kim:
A Systolic Architecture and Implementation of Feedback Network for Blind Source Separation. J. VLSI Signal Process. 47(2): 117-126 (2007) - Marcio Juliato, Guido Araujo, Julio López, Ricardo Dahab:
A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over F2163 using Gaussian Normal Bases. J. VLSI Signal Process. 47(1): 59-76 (2007) - Andrew Kinane, Noel E. O'Connor:
Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse. J. VLSI Signal Process. 47(2): 127-152 (2007) - Roman C. Kordasiewicz, Shahram Shirani:
On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC. J. VLSI Signal Process. 47(2): 93-102 (2007) - Roman C. Kordasiewicz, Shahram Shirani:
On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC. J. VLSI Signal Process. 47(3): 189-199 (2007) - Yi-Hsuan Lee, Cheng Chen:
An Efficient Code Generation Algorithm for Non-orthogonal DSP Architecture. J. VLSI Signal Process. 47(3): 281-296 (2007) - Sze Wei Lee, Soon-Chieh Lim:
An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems. J. VLSI Signal Process. 47(3): 201-221 (2007) - Mateusz Majer, Jürgen Teich, Ali Ahmadinia, Christophe Bobda:
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer. J. VLSI Signal Process. 47(1): 15-31 (2007) - Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre:
A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration. J. VLSI Signal Process. 47(3): 297-315 (2007) - Máire McLoone, Ciaran McIvor:
High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function. J. VLSI Signal Process. 47(1): 47-57 (2007) - Jun-Hee Mun, Shung Han Cho, Sangjin Hong:
Flexible Controller Design and Its Application for Concurrent Execution of Buffer Centric Dataflows. J. VLSI Signal Process. 47(3): 233-257 (2007) - T. Sansaloni, A. Perez-Pascual, Vicente Torres-Carot, Javier Valls:
Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs. J. VLSI Signal Process. 47(2): 183-187 (2007) - David B. Thomas, Wayne Luk:
High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices. J. VLSI Signal Process. 47(1): 77-92 (2007) - Chun Xue, Zili Shao, Edwin Hsing-Mean Sha:
Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping. J. VLSI Signal Process. 47(2): 153-167 (2007)
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