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Publication search results
found 65 matches
- 2013
- Sanghoon Lee, James Tuck:
Automatic parallelization of fine-grained metafunctions on a chip multiprocessor. ACM Trans. Archit. Code Optim. 10(4): 30:1-30:26 (2013) - Jung Ho Ahn, Young Hoon Son, John Kim:
Scalable high-radix router microarchitecture using a network switch organization. ACM Trans. Archit. Code Optim. 10(3): 17:1-17:25 (2013) - Adrià Armejach, J. Rubén Titos Gil, Anurag Negi, Osman S. Unsal, Adrián Cristal:
Techniques to improve performance in requester-wins hardware transactional memory. ACM Trans. Archit. Code Optim. 10(4): 42:1-42:25 (2013) - Ali Bakhoda, John Kim, Tor M. Aamodt:
Designing on-chip networks for throughput accelerators. ACM Trans. Archit. Code Optim. 10(3): 21:1-21:35 (2013) - Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors:
Designing a practical data filter cache to improve both energy efficiency and performance. ACM Trans. Archit. Code Optim. 10(4): 54:1-54:25 (2013) - Rajkishore Barik, Jisheng Zhao, Vivek Sarkar:
A decoupled non-SSA global register allocation using bipartite liveness graphs. ACM Trans. Archit. Code Optim. 10(4): 63:1-63:24 (2013) - Michela Becchi, Patrick Crowley:
A-DFA: A Time- and Space-Efficient DFA Compression Algorithm for Fast Regular Expression Evaluation. ACM Trans. Archit. Code Optim. 10(1): 4:1-4:26 (2013) - Yosi Ben-Asher, Nadav Rotem:
Hybrid type legalization for a sparse SIMD instruction set. ACM Trans. Archit. Code Optim. 10(3): 11:1-11:14 (2013) - Maximilien Breughe, Lieven Eeckhout:
Selecting representative benchmark inputs for exploring microprocessor design spaces. ACM Trans. Archit. Code Optim. 10(4): 37:1-37:24 (2013) - Rong Chen, Haibo Chen:
Tiled-MapReduce: Efficient and Flexible MapReduce Processing on Multicore with Tiling. ACM Trans. Archit. Code Optim. 10(1): 3:1-3:30 (2013) - Yunji Chen, Tianshi Chen, Ling Li, Ruiyang Wu, Dao-Fu Liu, Weiwu Hu:
Deterministic Replay Using Global Clock. ACM Trans. Archit. Code Optim. 10(1): 1:1-1:28 (2013) - Long Chen, Yanan Cao, Zhao Zhang:
E3CC: A memory error protection scheme with novel address mapping for subranked and low-power memories. ACM Trans. Archit. Code Optim. 10(4): 32:1-32:22 (2013) - Chien-Chi Chen, Sheng-De Wang:
An efficient multicharacter transition string-matching engine based on the aho-corasick algorithm. ACM Trans. Archit. Code Optim. 10(4): 25:1-25:22 (2013) - Tanima Dey, Wei Wang, Jack W. Davidson, Mary Lou Soffa:
ReSense: Mapping dynamic workloads of colocated multithreaded applications using resource sensitivity. ACM Trans. Archit. Code Optim. 10(4): 41:1-41:25 (2013) - Xiangyu Dong, Norman P. Jouppi, Yuan Xie:
A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies. ACM Trans. Archit. Code Optim. 10(4): 23:1-23:22 (2013) - Christophe Dubach, Timothy M. Jones, Edwin V. Bonilla:
Dynamic microarchitectural adaptation using machine learning. ACM Trans. Archit. Code Optim. 10(4): 31:1-31:28 (2013) - Naznin Fauzia, Venmugil Elango, Mahesh Ravishankar, J. Ramanujam, Fabrice Rastello, Atanas Rountev, Louis-Noël Pouchet, P. Sadayappan:
Beyond reuse distance analysis: Dynamic analysis for characterization of data locality potential. ACM Trans. Archit. Code Optim. 10(4): 53:1-53:29 (2013) - Viacheslav V. Fedorov, Sheng Qiu, A. L. Narasimha Reddy, Paul V. Gratz:
ARI: Adaptive LLC-memory traffic management. ACM Trans. Archit. Code Optim. 10(4): 46:1-46:19 (2013) - Peter Gavin, David B. Whalley, Magnus Själander:
Reducing instruction fetch energy in multi-issue processors. ACM Trans. Archit. Code Optim. 10(4): 64:1-64:24 (2013) - Cecilia González-Alvarez, Jennifer B. Sartor, Carlos Álvarez, Daniel Jiménez-González, Lieven Eeckhout:
Accelerating an application domain with specialized functional units. ACM Trans. Archit. Code Optim. 10(4): 47:1-47:25 (2013) - Andrei Hagiescu, Bing Liu, R. Ramanathan, Sucheendra K. Palaniappan, Zheng Cui, Bipasa Chattopadhyay, P. S. Thiagarajan, Weng-Fai Wong:
GPU code generation for ODE-based applications with phased shared-data access patterns. ACM Trans. Archit. Code Optim. 10(4): 55:1-55:19 (2013) - Kyuseung Han, Junwhan Ahn, Kiyoung Choi:
Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA. ACM Trans. Archit. Code Optim. 10(2): 8:1-8:25 (2013) - Libo Huang, Zhiying Wang, Nong Xiao, Yongwen Wang, Qiang Dou:
Adaptive communication mechanism for accelerating MPI functions in NoC-based multicore processors. ACM Trans. Archit. Code Optim. 10(3): 18:1-18:25 (2013) - Michael R. Jantz, Prasad A. Kulkarni:
Exploring single and multilevel JIT compilation policy for modern machines. ACM Trans. Archit. Code Optim. 10(4): 22:1-22:29 (2013) - Myeongjae Jeon, Conglong Li, Alan L. Cox, Scott Rixner:
Reducing DRAM row activations with eager read/write clustering. ACM Trans. Archit. Code Optim. 10(4): 43:1-43:25 (2013) - Yeonghun Jeong, Seongseok Seo, Jongeun Lee:
Evaluator-executor transformation for efficient pipelining of loops with conditionals. ACM Trans. Archit. Code Optim. 10(4): 62:1-62:23 (2013) - Lei Jiang, Yu Du, Bo Zhao, Youtao Zhang, Bruce R. Childers, Jun Yang:
Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory. ACM Trans. Archit. Code Optim. 10(2): 7:1-7:25 (2013) - Chuntao Jiang, Zhibin Yu, Hai Jin, Cheng-Zhong Xu, Lieven Eeckhout, Wim Heirman, Trevor E. Carlson, Xiaofei Liao:
PCantorSim: Accelerating parallel architecture simulation through fractal-based sampling. ACM Trans. Archit. Code Optim. 10(4): 49:1-49:24 (2013) - Motohiro Kawahito, Hideaki Komatsu, Takao Moriyama, Hiroshi Inoue, Toshio Nakatani:
Idiom recognition framework using topological embedding. ACM Trans. Archit. Code Optim. 10(3): 13:1-13:34 (2013) - Christoph Kerschbaumer, Eric Hennigan, Per Larsen, Stefan Brunthaler, Michael Franz:
Information flow tracking meets just-in-time compilation. ACM Trans. Archit. Code Optim. 10(4): 38:1-38:25 (2013)
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