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Publication search results
found 95 matches
- 2000
- Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
A scheme for multiple on-chip signature checking for embedded SRAMS. J. Syst. Archit. 46(2): 181-199 (2000) - Gail-Joon Ahn:
Role-based access control in DCOM. J. Syst. Archit. 46(13): 1175-1184 (2000) - Yousef J. Al-Houmaily, Panos K. Chrysanthis:
An atomic commit protocol for gigabit-networked distributed database systems. J. Syst. Archit. 46(9): 809-833 (2000) - Mayez A. Al-Mouhamed, Adel Al-Massarani:
Scheduling optimization through iterative refinement. J. Syst. Archit. 46(10): 851-871 (2000) - Abdullah I. Al-Shoshan, Mohammad A. Aloqeely:
Systolic arrays architecture for computing the time-frequency spectrum. J. Syst. Archit. 46(6): 513-517 (2000) - Abdullah I. AlMojel, Tarek A. El-Ghazawi, Thomas L. Sterling:
Characterizing and representing workloads for parallel computer architectures. J. Syst. Archit. 46(1): 23-37 (2000) - Novruz M. Allahverdi, Sirzad S. Kahramanli, Kayhan Erciyes:
A fault tolerant routing algorithm based on cube algebra for hypercube systems. J. Syst. Archit. 46(2): 201-205 (2000) - D. De Almeida, Patrick Kellert:
Markovian and analytical models for multiple bus multiprocessor systems with memory blockings. J. Syst. Archit. 46(5): 455-477 (2000) - Davide Anguita, Andrea Boni, Giancarlo Parodi:
A case study of a distributed high-performance computing system for neurocomputing. J. Syst. Archit. 46(5): 429-438 (2000) - James Aweya:
On the design of IP routers Part 1: Router architectures. J. Syst. Archit. 46(6): 483-511 (2000) - A. K. Bandyopadhyay, J. Bandyopadhyay:
On the derivation of a correct deadlock free communication kernel for loop connected message passing architecture from its user's specification. J. Syst. Archit. 46(13): 1257-1261 (2000) - Andrew Bardsley, Doug A. Edwards:
Synthesising an asynchronous DMA controller with Balsa. J. Syst. Archit. 46(14): 1309-1319 (2000) - S. Bhattacharya, Mita Nasipuri:
Traffic analysis in a double grain Dataflow array processor. J. Syst. Archit. 46(1): 97-101 (2000) - Giacomo Buonanno, Franco Fummi, Donatella Sciuto:
An extended-UIO-based method for protocol conformance testing. J. Syst. Archit. 46(3): 225-242 (2000) - Alan Burns, Divya Prasad, Andrea Bondavalli, Felicita Di Giandomenico, Krithi Ramamritham, John A. Stankovic, Lorenzo Strigini:
The meaning and role of value in scheduling flexible real-time systems. J. Syst. Archit. 46(4): 305-325 (2000) - José V. Busquets-Mataix, Daniel Gil, Pedro J. Gil, Andy J. Wellings:
Techniques to increase the schedulable utilization of cache-based preemptive real-time systems. J. Syst. Archit. 46(4): 357-378 (2000) - Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Symbolic forward/backward traversals of large finite state machines. J. Syst. Archit. 46(12): 1137-1158 (2000) - Giacomo Cabri, Letizia Leonardi, Franco Zambonelli:
Agents for information retrieval: Issues of mobility and coordination. J. Syst. Archit. 46(15): 1419-1433 (2000) - A. Castorino, Gianfranco Ciccarella:
Algorithms for real-time scheduling of error-cumulative tasks based on the imprecise computation approach. J. Syst. Archit. 46(7): 587-600 (2000) - Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Sharon Hu:
Efficient module selections for finding highly acceptable designs based on inclusion scheduling. J. Syst. Archit. 46(11): 1047-1071 (2000) - Tzung-Shi Chen, Chih-Yung Chang, Jang-Ping Sheu:
Efficient path-based multicast in wormhole-routed mesh networks. J. Syst. Archit. 46(10): 919-930 (2000) - Andrea Clematis, Gabriella Dodero, Vittoria Gianuzzi:
Efficient use of parallel libraries on heterogeneous Networks of Workstations. J. Syst. Archit. 46(8): 641-653 (2000) - Nabanita Das, Krishnendu Mukhopadhyaya, Jayasree Dattagupta:
O(n) routing in rearrangeable networks. J. Syst. Archit. 46(6): 529-542 (2000) - S. J. Davis, C. J. Elston, Paul A. Findlay:
Register bypassing in an asynchronous superscalar processor. J. Syst. Archit. 46(9): 749-764 (2000) - Ridha Djemal, Guy Mazaré, Rached Tourki:
Rapid prototyping of an ATM programmable associative operator. J. Syst. Archit. 46(13): 1159-1173 (2000) - Lieven Eeckhout, Henk Neefs, Koen De Bosschere:
Early design stage exploration of fixed-length block structured architectures. J. Syst. Archit. 46(15): 1469-1486 (2000) - Muhammet Fikret Ercan, Yu-Fai Fung, M. Suleyman Demokan:
Communication in a multi-layer MIMD system for computer vision. J. Syst. Archit. 46(14): 1349-1364 (2000) - Patricia González, José Carlos Cabaleiro, Tomás F. Pena:
On parallel solvers for sparse triangular systems. J. Syst. Archit. 46(8): 675-685 (2000) - Huiwei Guan, To-Yat Cheung:
Efficient approaches for constructing a massively parallel processing system. J. Syst. Archit. 46(13): 1185-1190 (2000) - Wolfgang Günther, Rolf Drechsler:
ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs. J. Syst. Archit. 46(14): 1321-1334 (2000)
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