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Publication search results
found 17 matches
- 2019
- Julián Caba, Fernando Rincón, Julio Dondo, Jesús Barba, Manuel J. Abaldea, Juan Carlos López:
Testing framework for on-board verification of HLS modules using grey-box technique and FPGA overlays. Integr. 68: 129-138 (2019) - Ferdinando Costanzo, Rocco Giofrè, Antonino Massari, Marziale Feudale, Andrea Suriani, Ernesto Limiti:
A MMIC power amplifier in GaN on Si technology for next generation Q band high throughput satellite systems. Integr. 68: 139-146 (2019) - Luca Crocetti, Luca Baldanzi, Matteo Bertolucci, Luca Sarti, Berardino Carnevale, Luca Fanucci:
A simulated approach to evaluate side-channel attack countermeasures for the Advanced Encryption Standard. Integr. 68: 80-86 (2019) - Farzad Daryabari, Abdulhamid Zahedi, Abbas Rezaei, Mohsen Hayati:
Gain-controlled noise-reduction LNA design using source-bulk resistors and double common-source topology. Integr. 68: 50-61 (2019) - Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Robert Schmidt, Thilo Pionteck, Alberto García Ortiz:
Simulation environment for link energy estimation in networks-on-chip with virtual channels. Integr. 68: 147-156 (2019) - Mohd Syafiq Mispan, Shengyu Duan, Basel Halak, Mark Zwolinski:
A reliable PUF in a dual function SRAM. Integr. 68: 12-21 (2019) - Lucas Lui Motta, Byron Alejandro Acuña Acurio, Nathália Figueiredo Tinoco Aniceto, Luís Geraldo P. Meloni:
Design and implementation of a digital down/up conversion directly from/to RF channels in HDL. Integr. 68: 30-37 (2019) - Kashif Nawaz, Léopold Van Brandt, Itamar Levi, François-Xavier Standaert, Denis Flandre:
A security oriented transient-noise simulation methodology: Evaluation of intrinsic physical noise of cryptographic designs. Integr. 68: 71-79 (2019) - Xiongfei Qu, Ruifeng Liu, Lingling Cao, Yuanzhi Zhang, Wenshen Wang, Huimin Liu, Chao Lu:
A 5.8 GHz digitally configurable DSRC RF-SoC transmitter for China ETC systems. Integr. 68: 99-107 (2019) - Subhabrata Roy, Abhijit Chandra:
Design of Narrow Transition Band Digital Filter: An Analytical Approach. Integr. 68: 38-49 (2019) - Young-Ho Seo, Sung-Ho Park, Dong-Wook Kim:
High-level hardware design of digital comparator with multiple inputs. Integr. 68: 157-165 (2019) - Roberto Sierra, Carlos Carreras, Gabriel Caffarena:
Witelo: Automated generation and timing characterization of distributed-control macroblocks for high-performance FPGA designs. Integr. 68: 1-11 (2019) - Shady M. Soliman, Mohammed A. Jaela, Abdelrhman M. Abotaleb, Youssef Hassan, Mohamed Abdelghany, Amr T. Abdel-Hamid, Khaled N. Salama, Hassan Mostafa:
FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping. Integr. 68: 108-121 (2019) - Zhen Wang, Jianhui Jiang, Tao Wang:
Failure probability analysis and critical node determination for approximate circuits. Integr. 68: 122-128 (2019) - Boran Wen, Qisheng Zhang, Xiao Zhao, Xiaolong Lv, Yongqing Wang:
Trade-offs among power consumption and other design parameters of two-stage recycling folded cascode OTA that using embedded cascode current buffer compensation technology. Integr. 68: 62-70 (2019) - Yaoyao Ye, Zhe Zhang:
A thermal-sensitive design of a 3D torus-based optical NoC architecture. Integr. 68: 22-29 (2019) - Monir Zaman, Mustafa M. Shihab, Ayse K. Coskun, Yiorgos Makris:
CAPE: A cross-layer framework for accurate microprocessor power estimation. Integr. 68: 87-98 (2019)
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