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@article{DBLP:journals/integration/CabaRDBAL19,
  author       = {Juli{\'{a}}n Caba and
                  Fernando Rinc{\'{o}}n and
                  Julio Dondo and
                  Jes{\'{u}}s Barba and
                  Manuel J. Abaldea and
                  Juan Carlos L{\'{o}}pez},
  title        = {Testing framework for on-board verification of {HLS} modules using
                  grey-box technique and {FPGA} overlays},
  journal      = {Integr.},
  volume       = {68},
  pages        = {129--138},
  year         = {2019},
  url          = {https://doi.org/10.1016/j.vlsi.2019.06.011},
  doi          = {10.1016/J.VLSI.2019.06.011},
  timestamp    = {Tue, 29 Dec 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/CabaRDBAL19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/CostanzoGMFSL19,
  author       = {Ferdinando Costanzo and
                  Rocco Giofr{\`{e}} and
                  Antonino Massari and
                  Marziale Feudale and
                  Andrea Suriani and
                  Ernesto Limiti},
  title        = {A {MMIC} power amplifier in GaN on Si technology for next generation
                  {Q} band high throughput satellite systems},
  journal      = {Integr.},
  volume       = {68},
  pages        = {139--146},
  year         = {2019},
  url          = {https://doi.org/10.1016/j.vlsi.2019.06.007},
  doi          = {10.1016/J.VLSI.2019.06.007},
  timestamp    = {Tue, 21 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/CostanzoGMFSL19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/CrocettiBBSCF19,
  author       = {Luca Crocetti and
                  Luca Baldanzi and
                  Matteo Bertolucci and
                  Luca Sarti and
                  Berardino Carnevale and
                  Luca Fanucci},
  title        = {A simulated approach to evaluate side-channel attack countermeasures
                  for the Advanced Encryption Standard},
  journal      = {Integr.},
  volume       = {68},
  pages        = {80--86},
  year         = {2019},
  url          = {https://doi.org/10.1016/j.vlsi.2019.06.005},
  doi          = {10.1016/J.VLSI.2019.06.005},
  timestamp    = {Wed, 07 Dec 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/CrocettiBBSCF19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/DaryabariZRH19,
  author       = {Farzad Daryabari and
                  Abdulhamid Zahedi and
                  Abbas Rezaei and
                  Mohsen Hayati},
  title        = {Gain-controlled noise-reduction {LNA} design using source-bulk resistors
                  and double common-source topology},
  journal      = {Integr.},
  volume       = {68},
  pages        = {50--61},
  year         = {2019},
  url          = {https://doi.org/10.1016/j.vlsi.2019.06.003},
  doi          = {10.1016/J.VLSI.2019.06.003},
  timestamp    = {Fri, 09 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/DaryabariZRH19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/JosephBHSPO19,
  author       = {Jan Moritz Joseph and
                  Lennart Bamberg and
                  Imad Hajjar and
                  Robert Schmidt and
                  Thilo Pionteck and
                  Alberto Garc{\'{\i}}a Ortiz},
  title        = {Simulation environment for link energy estimation in networks-on-chip
                  with virtual channels},
  journal      = {Integr.},
  volume       = {68},
  pages        = {147--156},
  year         = {2019},
  url          = {https://doi.org/10.1016/j.vlsi.2019.05.005},
  doi          = {10.1016/J.VLSI.2019.05.005},
  timestamp    = {Thu, 16 Jun 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/JosephBHSPO19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/MispanDHZ19,
  author       = {Mohd Syafiq Mispan and
                  Shengyu Duan and
                  Basel Halak and
                  Mark Zwolinski},
  title        = {A reliable {PUF} in a dual function {SRAM}},
  journal      = {Integr.},
  volume       = {68},
  pages        = {12--21},
  year         = {2019},
  url          = {https://doi.org/10.1016/j.vlsi.2019.06.001},
  doi          = {10.1016/J.VLSI.2019.06.001},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/MispanDHZ19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/MottaAAM19,
  author       = {Lucas Lui Motta and
                  Byron Alejandro Acu{\~{n}}a Acurio and
                  Nath{\'{a}}lia Figueiredo Tinoco Aniceto and
                  Lu{\'{\i}}s Geraldo P. Meloni},
  title        = {Design and implementation of a digital down/up conversion directly
                  from/to {RF} channels in {HDL}},
  journal      = {Integr.},
  volume       = {68},
  pages        = {30--37},
  year         = {2019},
  url          = {https://doi.org/10.1016/j.vlsi.2019.05.006},
  doi          = {10.1016/J.VLSI.2019.05.006},
  timestamp    = {Mon, 05 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/MottaAAM19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/NawazBLSF19,
  author       = {Kashif Nawaz and
                  L{\'{e}}opold Van Brandt and
                  Itamar Levi and
                  Fran{\c{c}}ois{-}Xavier Standaert and
                  Denis Flandre},
  title        = {A security oriented transient-noise simulation methodology: Evaluation
                  of intrinsic physical noise of cryptographic designs},
  journal      = {Integr.},
  volume       = {68},
  pages        = {71--79},
  year         = {2019},
  url          = {https://doi.org/10.1016/j.vlsi.2019.06.006},
  doi          = {10.1016/J.VLSI.2019.06.006},
  timestamp    = {Wed, 07 Dec 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/NawazBLSF19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/QuLCZWLL19,
  author       = {Xiongfei Qu and
                  Ruifeng Liu and
                  Lingling Cao and
                  Yuanzhi Zhang and
                  Wenshen Wang and
                  Huimin Liu and
                  Chao Lu},
  title        = {A 5.8{\unicode{8239}}GHz digitally configurable {DSRC} RF-SoC transmitter
                  for China {ETC} systems},
  journal      = {Integr.},
  volume       = {68},
  pages        = {99--107},
  year         = {2019},
  url          = {https://doi.org/10.1016/j.vlsi.2019.06.010},
  doi          = {10.1016/J.VLSI.2019.06.010},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/QuLCZWLL19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/RoyC19,
  author       = {Subhabrata Roy and
                  Abhijit Chandra},
  title        = {Design of Narrow Transition Band Digital Filter: An Analytical Approach},
  journal      = {Integr.},
  volume       = {68},
  pages        = {38--49},
  year         = {2019},
  url          = {https://doi.org/10.1016/j.vlsi.2019.06.002},
  doi          = {10.1016/J.VLSI.2019.06.002},
  timestamp    = {Mon, 26 Jun 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/RoyC19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/SeoPK19,
  author       = {Young{-}Ho Seo and
                  Sung{-}Ho Park and
                  Dong{-}Wook Kim},
  title        = {High-level hardware design of digital comparator with multiple inputs},
  journal      = {Integr.},
  volume       = {68},
  pages        = {157--165},
  year         = {2019},
  url          = {https://doi.org/10.1016/j.vlsi.2019.04.003},
  doi          = {10.1016/J.VLSI.2019.04.003},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/SeoPK19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/SierraCC19,
  author       = {Roberto Sierra and
                  Carlos Carreras and
                  Gabriel Caffarena},
  title        = {Witelo: Automated generation and timing characterization of distributed-control
                  macroblocks for high-performance {FPGA} designs},
  journal      = {Integr.},
  volume       = {68},
  pages        = {1--11},
  year         = {2019},
  url          = {https://doi.org/10.1016/j.vlsi.2019.05.001},
  doi          = {10.1016/J.VLSI.2019.05.001},
  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/SierraCC19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/SolimanJAHAASM19,
  author       = {Shady M. Soliman and
                  Mohammed A. Jaela and
                  Abdelrhman M. Abotaleb and
                  Youssef Hassan and
                  Mohamed Abdelghany and
                  Amr T. Abdel{-}Hamid and
                  Khaled N. Salama and
                  Hassan Mostafa},
  title        = {{FPGA} implementation of dynamically reconfigurable IoT security module
                  using algorithm hopping},
  journal      = {Integr.},
  volume       = {68},
  pages        = {108--121},
  year         = {2019},
  url          = {https://doi.org/10.1016/j.vlsi.2019.06.004},
  doi          = {10.1016/J.VLSI.2019.06.004},
  timestamp    = {Mon, 05 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/SolimanJAHAASM19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/WangJW19,
  author       = {Zhen Wang and
                  Jianhui Jiang and
                  Tao Wang},
  title        = {Failure probability analysis and critical node determination for approximate
                  circuits},
  journal      = {Integr.},
  volume       = {68},
  pages        = {122--128},
  year         = {2019},
  url          = {https://doi.org/10.1016/j.vlsi.2019.05.008},
  doi          = {10.1016/J.VLSI.2019.05.008},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/WangJW19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/WenZZLW19,
  author       = {Boran Wen and
                  Qisheng Zhang and
                  Xiao Zhao and
                  Xiaolong Lv and
                  Yongqing Wang},
  title        = {Trade-offs among power consumption and other design parameters of
                  two-stage recycling folded cascode {OTA} that using embedded cascode
                  current buffer compensation technology},
  journal      = {Integr.},
  volume       = {68},
  pages        = {62--70},
  year         = {2019},
  url          = {https://doi.org/10.1016/j.vlsi.2019.06.009},
  doi          = {10.1016/J.VLSI.2019.06.009},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/WenZZLW19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/YeZ19,
  author       = {Yaoyao Ye and
                  Zhe Zhang},
  title        = {A thermal-sensitive design of a 3D torus-based optical NoC architecture},
  journal      = {Integr.},
  volume       = {68},
  pages        = {22--29},
  year         = {2019},
  url          = {https://doi.org/10.1016/j.vlsi.2019.05.007},
  doi          = {10.1016/J.VLSI.2019.05.007},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/YeZ19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/ZamanSCM19,
  author       = {Monir Zaman and
                  Mustafa M. Shihab and
                  Ayse K. Coskun and
                  Yiorgos Makris},
  title        = {{CAPE:} {A} cross-layer framework for accurate microprocessor power
                  estimation},
  journal      = {Integr.},
  volume       = {68},
  pages        = {87--98},
  year         = {2019},
  url          = {https://doi.org/10.1016/j.vlsi.2019.05.002},
  doi          = {10.1016/J.VLSI.2019.05.002},
  timestamp    = {Fri, 09 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/ZamanSCM19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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