• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 56 matches

• 2016
• 
  Khaled E. Ahmed, Mohamed R. M. Rizk, Mohammed M. Farag:
  Overloaded CDMA interconnect for Network-on-Chip (OCNoC). ReConFig 2016: 1-7
• 
  Atil U. Ay, Erdinç Öztürk, Francisco Rodríguez-Henríquez, Erkay Savas:
  Design and implementation of a constant-time FPGA accelerator for fast elliptic curve cryptography. ReConFig 2016: 1-8
• 
  Matej Bartik, Sven Ubik, Pavel Kubalík:
  A novel and efficient method to initialize FPGA embedded memory content in asymptotically constant time. ReConFig 2016: 1-6
• 
  Andreas Becher, Jutta Pirkl, Achim Herrmann, Jürgen Teich, Stefan Wildermann:
  Hybrid energy-aware reconfiguration management on Xilinx Zynq SoCs. ReConFig 2016: 1-7
• 
  Andreas Becher, Stefan Wildermann, Moritz Mühlenthaler, Jürgen Teich:
  ReOrder: Runtime datapath generation for high-throughput multi-stream processing. ReConFig 2016: 1-8
• 
  Skip Booth:
  Keynote 2 - FPGAs in the datacenter - A software view. ReConFig 2016: 1
• 
  Benjamin R. Buhrow, William J. Goetzinger, Barry K. Gilbert:
  1 Tb/s anti-replay protection with 20-port on-chip RAM memory in FPGAs. ReConFig 2016: 1-8
• 
  Qianqiao Chen, Vaibhawa Mishra, Georgios Zervas:
  Reconfigurable computing for network function virtualization: A protocol independent switch. ReConFig 2016: 1-6
• 
  Tiziana Fanni, Luigi Raffo:
  Coarse grain reconfiguration: Power estimation and management flow for hybrid gated systems. ReConFig 2016: 1-4
• 
  Farnoud Farahmand, Ekawat Homsirikamol, Kris Gaj:
  A Zynq-based testbed for the experimental benchmarking of algorithms competing in cryptographic contests. ReConFig 2016: 1-7
• 
  Paolo Di Febbo, Stefano Mattoccia, Carlo Dal Mutto:
  Real-time image distortion correction: Analysis and evaluation of FPGA-compatible algorithms. ReConFig 2016: 1-6
• 
  João Canas Ferreira, Jose Fonseca:
  An FPGA implementation of a long short-term memory neural network. ReConFig 2016: 1-8
• 
  Kledermon Garcia, Duarte Lopes de Oliveira, Roberto d'Amore, Lester de Abreu Faria, Joao Luis V. Oliveira:
  FPGA implementation of optimized XBM specifications by transformation for AFSMs. ReConFig 2016: 1-6
• 
  Robért Glein, Florian Rittner, Albert Heuberger:
  Adaptive single-event effect mitigation for dependable processing systems. ReConFig 2016: 1-8
• 
  Akihiko Hamada, Hiroki Matsutani:
  Design and implementation of hardware cache mechanism and NIC for column-oriented databases. ReConFig 2016: 1-6
• 
  Travis Haroldsen, Brent E. Nelson, Brad L. Hutchings:
  Packing a modern Xilinx FPGA using RapidSmith. ReConFig 2016: 1-6
• 
  Sam M. H. Ho, Maolin Wang, Ho-Cheung Ng, Hayden Kwok-Hay So:
  Towards FPGA-assisted spark: An SVM training acceleration case study. ReConFig 2016: 1-6
• 
  Jaco A. Hofmann, Jens Korinth, Andreas Koch:
  A scalable latency-insensitive architecture for FPGA-accelerated semi-global matching in stereo vision applications. ReConFig 2016: 1-8
• 
  Ernst Joachim Houtgast, Vlad Mihai Sima, Giacomo Marchiori, Koen Bertels, Zaid Al-Ars:
  Power-efficiency analysis of accelerated BWA-MEM implementations on heterogeneous computing platforms. ReConFig 2016: 1-8
• 
  Andres Jacoby, Daniel Llamocca:
  Dual fixed-point CORDIC processor: Architecture and FPGA implementation. ReConFig 2016: 1-8
• 
  Jan Moritz Joseph, Tobias Winker, Kristian Ehlers, Christopher Blochwitz, Thilo Pionteck:
  Hardware-accelerated pose estimation for embedded systems using Vivado HLS. ReConFig 2016: 1-7
• 
  Lukas Johannes Jung, Christian Hochberger:
  Optimal processor interface for CGRA-based accelerators implemented on FPGAs. ReConFig 2016: 1-7
• 
  Bernhard Jungk, Marc Stöttinger:
  Hobbit - Smaller but faster than a dwarf: Revisiting lightweight SHA-3 FPGA implementations. ReConFig 2016: 1-7
• 
  Tobias Kalb, Diana Göhringer:
  Enabling dynamic and partial reconfiguration in Xilinx SDSoC. ReConFig 2016: 1-7
• 
  Rasha Karakchi, Jordan A. Bradshaw, Jason D. Bakos:
  High-level synthesis of a genomic database search engine. ReConFig 2016: 1-6
• 
  Robert Karam, Tamzidul Hoque, Sandip Ray, Mark M. Tehranipoor, Swarup Bhunia:
  Technical demonstration session: Software toolflow for FPGA bitstream obfuscation. ReConFig 2016: 1-2
• 
  Robert Karam, Tamzidul Hoque, Sandip Ray, Mark M. Tehranipoor, Swarup Bhunia:
  Robust bitstream protection in FPGA-based systems through low-overhead obfuscation. ReConFig 2016: 1-8
• 
  Habib ul Hasan Khan, Diana Göhringer:
  FPGA debugging by a device start and stop approach. ReConFig 2016: 1-6
• 
  Pham Nam Khanh, Khin Mi Mi Aung, Akash Kumar:
  Automatic framework to generate reconfigurable accelerators for option pricing applications. ReConFig 2016: 1-8
• 
  Gundolf Kiefer, Matthias Vahl, Julian Sarcher, Michael Schaeferling:
  A configurable architecture for the generalized hough transform applied to the analysis of huge aerial images and to traffic sign detection. ReConFig 2016: 1-7

skipping 26 more matches