• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 78 matches

• 2009
• 
  Mathieu Allard, Patrick Grogan, Jean-Pierre David:
  A Scalable Architecture for Multivariate Polynomial Evaluation on FPGA. ReConFig 2009: 107-112
• 
  Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez:
  Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. ReConFig 2009: 201-206
• 
  Rafael A. Arce-Nazario, Edusmildo Orozco, Dorothy Bollman:
  A Systolic Array Based Architecture for Implementing Multivariate Polynomial Interpolation Tasks. ReConFig 2009: 77-82
• 
  Mark G. Arnold, Jung H. Cho:
  Parallax-Docking and Reconfiguration of Field Programmable Robot Arrays Using an Intermittently-Powered One-Hot Controller. ReConFig 2009: 398-403
• 
  Arghavan Asad, Amir Ehsani Zonouz, Mehrdad Seyrafi, Mohsen Soryani, Mahmood Fathy:
  Modeling and Analyzing of Blocking Time Effects on Power Consumption in Network-on-Chips. ReConFig 2009: 290-295
• 
  Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, Jaime Jimenez:
  PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems. ReConFig 2009: 54-58
• 
  Malte Baesler, Thomas Teufel:
  FPGA Implementation of a Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier. ReConFig 2009: 6-11
• 
  Brian Baldwin, William P. Marnane, Robert Granger:
  Reconfigurable Hardware Implementation of Arithmetic Modulo Minimal Redundancy Cyclotomic Primes for ECC. ReConFig 2009: 255-260
• 
  Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane:
  Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig 2009: 213-218
• 
  Nathalie Bochard, Florent Bernard, Viktor Fischer:
  Observing the Randomness in RO-Based TRNG. ReConFig 2009: 237-242
• 
  Hector Borrayo-Sandoval, Ramón Parra-Michel, Luis F. Gonzalez-Perez, Fernando Landeros Printzen, Claudia Feregrino Uribe:
  Design and Implementation of a Configurable Interleaver/Deinterleaver for Turbo Codes in 3GPP Standard. ReConFig 2009: 320-325
• 
  Julien Bringer, Hervé Chabanne, Jean-Luc Danger:
  Protecting the NOEKEON Cipher against SCARE Attacks in FPGAs by Using Dynamic Implementations. ReConFig 2009: 183-188
• 
  Eduardo Cabal-Yepez, Roque Alfredo Osornio-Rios, René de Jesús Romero-Troncoso, J. R. Razo-Hernandez, R. Lopez-Garcia:
  FPGA-Based Online Induction Motor Multiple-Fault Detection with Fused FFT and Wavelet Analysis. ReConFig 2009: 101-106
• 
  C. Yesid E. Castro, Carlos H. Llanos, Walter de Britto Vidal Filho, Leandro dos Santos Coelho:
  Fuzzy Control for Cyclist Robot Stability Using FPGAs. ReConFig 2009: 410-415
• 
  Leonard Colavito, Dennis Silage:
  Efficient PGA LFSR Implementation Whitens Pseudorandom Numbers. ReConFig 2009: 308-313
• 
  Leonard Colavito, Dennis Silage:
  Composite Look-Up Table Gaussian Pseudo-Random Number Generator. ReConFig 2009: 314-319
• 
  Guillermo Conde, Gregory W. Donohoe, Siva Maheswaran:
  Low Power, Reconfigurable Computing Platform for Spacecraft. ReConFig 2009: 149-154
• 
  James Coole, John Robert Wernsing, Greg Stitt:
  A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation. ReConFig 2009: 143-148
• 
  Rachid Dafali, Jean-Philippe Diguet:
  Self-Adaptive Network Interface (SANI): Local Component of a NoC Configuration Manager. ReConFig 2009: 296-301
• 
  Siddhartha Datta, Ron Sass:
  Scalability Studies of the BLASTn Scan and Ungapped Extension Functions. ReConFig 2009: 131-136
• 
  Julien Delorme, Amor Nafkha, Pierre Leray, Christophe Moy:
  New OPBHWICAP Interface for Realtime Partial Reconfiguration of FPGA. ReConFig 2009: 386-391
• 
  Stefan Döbrich, Christian Hochberger:
  Effects of Simplistic Online Synthesis for AMIDAR Processors. ReConFig 2009: 433-438
• 
  Taho Dorta, Jaime Jimenez, José Luis Martín, Unai Bidarte, Armando Astarloa:
  Overview of FPGA-Based Multiprocessor Systems. ReConFig 2009: 273-278
• 
  Stephanie Drzevitzky, Uwe Kastens, Marco Platzner:
  Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. ReConFig 2009: 189-194
• 
  Mark E. Dunham, Zachary K. Baker, Matthew Stettler, Michael Pigue, Paul S. Graham, Eric N. Schmierer, John Power:
  High Efficiency Space-Based Software Radio Architectures: A Minimum Size, Weight, and Power TeraOps Processor. ReConFig 2009: 326-331
• 
  Ahmet Onur Durahim, Erkay Savas, Kazim Yumbul:
  Implementing a Protected Zone in a Reconfigurable Processor for Isolated Execution of Cryptographic Algorithms. ReConFig 2009: 207-212
• 
  Sven Eisenhardt, Thomas Schweizer, Andreas Bernauer, Tommy Kuhn, Wolfgang Rosenstiel:
  Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures. ReConFig 2009: 12-17
• 
  Laurent Gantel, Salah Layouni, Mohamed El Amine Benkhelifa, François Verdier, Stéphanie Chauvet:
  Multiprocessor Task Migration Implementation in a Reconfigurable Platform. ReConFig 2009: 362-367
• 
  Sergio Ruben Geninatti, José Ignacio Benavides Benítez, Manuel Hernandez Calviño, Nicolás Guil Mata, Juan Gómez-Luna:
  FPGA Implementation of the Generalized Hough Transform. ReConFig 2009: 172-177
• 
  Solmaz Ghaznavi, Catherine H. Gebotys, Reouven Elbaz:
  Efficient Technique for the FPGA Implementation of the AES MixColumns Transformation. ReConFig 2009: 219-224

skipping 48 more matches