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Publication search results
found 19 matches
- 2024
- Elias Barbudo, Thierry Grandpierre, Eva Dokládalová:
Latency-Accurate Models for Software Programmable Streaming Coarse-Grained Reconfigurable Hardware Architectures. HEART 2024: 133-134 - Federico Corradi, Zhanbo Shen, Hanqing Zhao, Nikolaos Alachiotis:
Accelerated Spiking Convolutional Neural Networks for Scalable Population Genomics. HEART 2024: 53-62 - Ce Guo, Haoran Wu, Wayne Luk:
Resource-Constraint Bayesian Optimization for Soft Processors on FPGAs. HEART 2024: 27-36 - Julian Haase, Nico Volkens, Diana Goehringer:
Embedded Security Accelerators within Network-on-Chip Environments. HEART 2024: 37-43 - Gento Hiruma, Mingyu Yang, Yang Li, Kazuo Sakiyama, Yuko Hara-Azumi:
High-Level Synthesis Countermeasure Using Threshold Implementation with Mixed Number of Shares. HEART 2024: 18-26 - Martin Langhammer, George A. Constantinides:
Soft GPGPU versus IP cores: Quantifying and Reducing the Performance Gap. HEART 2024: 44-52 - Maksim Levental, Arham Khan, Ryan Chard, Kyle Chard, Stephen Neuendorffer, Ian T. Foster:
An End-to-End Programming Model for AI Engine Architectures. HEART 2024: 135-136 - Maksim Levental, Arham Khan, Ryan Chard, Kazutomo Yoshii, Kyle Chard, Ian T. Foster:
BraggHLS: High-Level Synthesis for Low-Latency Deep Neural Networks for Experimental Science. HEART 2024: 10-17 - Ajay Kumar M, Vineet Kumar, Deepu John, Shreejith Shanker:
Implementation and analysis of custom instructions on RISC-V for Edge-AI applications. HEART 2024: 126-129 - Geetesh More, Suprio Ray, Kenneth B. Kent:
Learned Index Acceleration with FPGAs: A SMART Approach. HEART 2024: 71-80 - Ai Nozaki, Takuya Kojima, Hiroshi Nakamura, Hideki Takase:
MLIR-Based Homomorphic Encryption Compiler for GPU. HEART 2024: 130-132 - Raveena Raikar, Dirk Stroobandt:
LiquidMD: Optimizing Inter-die and Intra-die placement for 2.5D FPGA Architectures. HEART 2024: 90-98 - Juan Miguel De Haro Ruiz, Carlos Ávarez Martínez, Daniel Jiménez-González, Xavier Martorell Bofill:
Enabling high-level parallel programming on multi-FPGA clusters. HEART 2024: 1-9 - Yuxi Tan, Masaru Nishimura, Riadh Ben Abdelhamid, Bingjie Guo, Qixiang Gao, Yoshiki Yamaguchi:
Systolic Array-Based Many-Core Processor with Simultaneous Dual-Instruction Issuance. HEART 2024: 119-125 - Kate Thurmer, Vaughn Betz:
VIPER: A VTR Interface for Placement with Error Resilience. HEART 2024: 99-108 - Rikuya Tomii, Tetsu Narumi:
A Hardware Solver for Simultaneous Linear Equations with Multistage Interconnection Network. HEART 2024: 81-89 - Kaijie Wei, Hideharu Amano, Ryohei Niwase, Yoshiki Yamaguchi:
A data compressor for FPGA-based state vector quantum simulators. HEART 2024: 63-70 - Haoran Wei, Omkar Bhilare, Hamas Waqar, Jason Helge Anderson:
CAD Techniques for NoC-Connected Multi-CGRA Systems. HEART 2024: 109-118 - Lana Josipovic, Peipei Zhou, Shreejith Shanker, João M. P. Cardoso, Jason Anderson, Shibata Yuichiro:
Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2024, Porto, Portugal, June 19-21, 2024. ACM 2024 [contents]
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