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ORCID14th HEART 2024: Porto, Portugal
- Lana Josipovic, Peipei Zhou, Shreejith Shanker, João M. P. Cardoso, Jason Anderson, Shibata Yuichiro:
Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2024, Porto, Portugal, June 19-21, 2024. ACM 2024 - Juan Miguel De Haro Ruiz
, Carlos Álvarez-Martínez, Daniel Jiménez-González, Xavier Martorell Bofill:
Enabling high-level parallel programming on multi-FPGA clusters. 1-9 - Maksim Levental, Arham Khan, Ryan Chard, Kazutomo Yoshii, Kyle Chard, Ian T. Foster:
BraggHLS: High-Level Synthesis for Low-Latency Deep Neural Networks for Experimental Science. 10-17 - Gento Hiruma, Mingyu Yang, Yang Li, Kazuo Sakiyama, Yuko Hara-Azumi:
High-Level Synthesis Countermeasure Using Threshold Implementation with Mixed Number of Shares. 18-26 - Ce Guo, Haoran Wu, Wayne Luk:
Resource-Constraint Bayesian Optimization for Soft Processors on FPGAs. 27-36 - Julian Haase, Nico Volkens, Diana Goehringer:
Embedded Security Accelerators within Network-on-Chip Environments. 37-43 - Martin Langhammer, George A. Constantinides:
Soft GPGPU versus IP cores: Quantifying and Reducing the Performance Gap. 44-52 - Federico Corradi, Zhanbo Shen, Hanqing Zhao, Nikolaos Alachiotis:
Accelerated Spiking Convolutional Neural Networks for Scalable Population Genomics. 53-62 - Kaijie Wei, Hideharu Amano, Ryohei Niwase, Yoshiki Yamaguchi:
A data compressor for FPGA-based state vector quantum simulators. 63-70 - Geetesh More, Suprio Ray, Kenneth B. Kent:
Learned Index Acceleration with FPGAs: A SMART Approach. 71-80 - Rikuya Tomii, Tetsu Narumi:
A Hardware Solver for Simultaneous Linear Equations with Multistage Interconnection Network. 81-89 - Raveena Raikar, Dirk Stroobandt:
LiquidMD: Optimizing Inter-die and Intra-die placement for 2.5D FPGA Architectures. 90-98 - Kate Thurmer, Vaughn Betz:
VIPER: A VTR Interface for Placement with Error Resilience. 99-108 - Haoran Wei, Omkar Bhilare, Hamas Waqar, Jason Helge Anderson:
CAD Techniques for NoC-Connected Multi-CGRA Systems. 109-118 - Yuxi Tan, Masaru Nishimura, Riadh Ben Abdelhamid, Bingjie Guo, Qixiang Gao, Yoshiki Yamaguchi:
Systolic Array-Based Many-Core Processor with Simultaneous Dual-Instruction Issuance. 119-125 - Ajay Kumar M, Vineet Kumar, Deepu John, Shreejith Shanker:
Implementation and analysis of custom instructions on RISC-V for Edge-AI applications. 126-129 - Ai Nozaki, Takuya Kojima, Hiroshi Nakamura, Hideki Takase:
MLIR-Based Homomorphic Encryption Compiler for GPU. 130-132 - Elias Barbudo, Thierry Grandpierre, Eva Dokládalová:
Latency-Accurate Models for Software Programmable Streaming Coarse-Grained Reconfigurable Hardware Architectures. 133-134 - Maksim Levental, Arham Khan, Ryan Chard, Kyle Chard, Stephen Neuendorffer, Ian T. Foster:
An End-to-End Programming Model for AI Engine Architectures. 135-136
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last updated on 2026-01-18 21:54 CET by the dblp team
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