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Publication search results
found 104 matches
- 1999
- Mostafa I. H. Abd-El-Barr, Yanging Xu, Carl McCrosky:
Transistor Stuck-Open Fault Detection in Multilevel CMOS Circuits. Great Lakes Symposium on VLSI 1999: 388- - Hoda S. Abdel-Aty-Zohdy, Mahmoud Al-Nsour:
Digital Neural Processing Unit for Electronic Nose. Great Lakes Symposium on VLSI 1999: 236-237 - Emrah Acar, Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi:
S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric. Great Lakes Symposium on VLSI 1999: 60-63 - Md. Altaf-Ul-Amin, Zahari Mohamed Darus:
VHDL Design of a Test Processor Based on Mixed-Mode Test Generation. Great Lakes Symposium on VLSI 1999: 244- - Lim Chu Aun, S. M. Rezaul Hasan:
An all Digital BiCMOS Phase Lock Loop for VLSI Processors. Great Lakes Symposium on VLSI 1999: 318-320 - R. Balakrishnan, Richard F. Hobson:
A Greedy Router with Technology Targetable Output. Great Lakes Symposium on VLSI 1999: 252-255 - Subhashini Balakrishnan, Sofiène Tahar:
A Hierarchical Approach to the Formal Verification of Embedded Systems Using MDGs. Great Lakes Symposium on VLSI 1999: 284-287 - Daniel Berzon, Terry J. Fountain:
A Memory Design in QCAs using the SQUARES Formalism. Great Lakes Symposium on VLSI 1999: 166- - Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin:
The Design of a Register Renaming Unit. Great Lakes Symposium on VLSI 1999: 34-37 - Stephen A. Blythe, Robert A. Walker:
Efficiently Searching the Optimal Design Space. Great Lakes Symposium on VLSI 1999: 192- - Tom P. E. Broekaert, Berinder Brar, Frank J. Morris, Alan C. Seabaugh, Gary A. Frazier:
Resonant Tunneling Technology for Mixed Signal and Digital Circuits in the 10-100 GHz Domain. Great Lakes Symposium on VLSI 1999: 123- - Anna Maria Brosa, Joan Figueras:
On Optimizing Test Strategies for Analog Cells. Great Lakes Symposium on VLSI 1999: 92-96 - Kanad Chakraborty, Natesan Venkateswaran:
Congestion Mitigation During Placement. Great Lakes Symposium on VLSI 1999: 228-229 - Yuyu Chang, John Choma Jr., Jack Wills:
The Design of Cmos Gigahertz-Band Continuous-Time Active Lowpass Filters with Q-Enhancement Circuits. Great Lakes Symposium on VLSI 1999: 358-361 - Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Sharon Hu:
Efficient Algorithms for Finding Highly Acceptable Designs Based on Module-Utility Selections. Great Lakes Symposium on VLSI 1999: 128-131 - Samit Chaudhuri, Robert A. Walker:
Bounding Algorithms for Design Space Exploration. Great Lakes Symposium on VLSI 1999: 234-235 - Daniel Chillet, Olivier Sentieys, Michel Corazza:
Memory Unit Design for Real Time DSP Applications. Great Lakes Symposium on VLSI 1999: 260- - Roberto Corgnati, Enrico Macii, Massimo Poncino:
Clustered Table-Based Macromodels for RTL Power Estimation. Great Lakes Symposium on VLSI 1999: 354-357 - Gianluca Cornetta, Jordi Cortadella:
A Radix-16 SRT Division Unit with Speculation of the Quotient Digits. Great Lakes Symposium on VLSI 1999: 74-77 - Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
ALPS: A Peak Power Estimation Tool for Sequential Circuits. Great Lakes Symposium on VLSI 1999: 350-353 - David Crawley:
A Multilevel Cache Memory Architecture for Nanoelectronics. Great Lakes Symposium on VLSI 1999: 346- - Jim E. Crenshaw, Majid Sarrafzadeh, Prithviraj Banerjee, Pradeep Prabhakaran:
An Incremental Floorplanner. Great Lakes Symposium on VLSI 1999: 248-251 - Árpád Csurgay, Craig S. Lent, Wolfgang Porod:
Why is Time-Varying Control Necessary for Signal Processing with Locally-Connected Quantum-Dot Arrays? Great Lakes Symposium on VLSI 1999: 122- - H.-Ch. Dahmen, Uwe Gläser, Zoran Stamenkovic:
Modell Evaluation Using Genetic Manipulation Techniques. Great Lakes Symposium on VLSI 1999: 224-225 - Travis E. Doom, Anthony S. Wojcik, Moon-Jung Chung:
Design Recovery for Incomplete Combinational Logic. Great Lakes Symposium on VLSI 1999: 184-187 - Khaled M. Elleithy, E. G. Abd-El-Fattah:
A Genetic Algorithm for Register Allocation. Great Lakes Symposium on VLSI 1999: 226-227 - James C. Ellenbogen:
Advances Toward Molecular-Scale Electronic Digital Logic Circuits: A Review and Prospectus. Great Lakes Symposium on VLSI 1999: 392- - Robert L. Ewing:
Blending Symbolic Matrix and Dimensional Numerical Simulation Methodology for Mechatronics Systems. Great Lakes Symposium on VLSI 1999: 270-273 - Aamir A. Farooqui, Vojin G. Oklobdzija:
VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing. Great Lakes Symposium on VLSI 1999: 30-33 - Patrick Fay, Gary H. Bernstein, David H. Chow, Joel N. Schulman, Pinaki Mazumder, William Williamson III, Barry K. Gilbert:
Integration of InAs/AlSb/GaSb Resonant Interband Tunneling Diodes with Heterostructure Field-Effect Transistors for Ultra-High-Speed Digital Circuit Applications. Great Lakes Symposium on VLSI 1999: 162-165
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retrieved on 2024-08-24 10:29 CEST from data curated by the dblp team
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