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Publication search results
found 67 matches
- 2010
- Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton:
The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). FPGA 2010: 263-272 - Jason Helge Anderson, Chirag Ravishankar:
FPGA power reduction by guarded evaluation. FPGA 2010: 157-166 - Rahul Bhattacharya, Santosh Biswas, Siddhartha Mukhopadhyay:
FPGA based chip emulation system for test development and verification of analog and mixed signal circuits (abstract only). FPGA 2010: 284 - Huimin Bian, Andrew C. Ling, Alexander Choong, Jianwen Zhu:
Towards scalable placement for FPGAs. FPGA 2010: 147-156 - Mike Brugge, Mohammed A. S. Khalid:
Design and evaluation of a parameterizable NoC router for FPGAs (abstract only). FPGA 2010: 292 - Sunita Chandrasekaran, Shilpa Shanbagh, Douglas L. Maskell:
A dependency graph based methodology for parallelizing HLL applications on FPGA (abstract only). FPGA 2010: 286 - Zhimin Chen, Richard Neil Pittman, Alessandro Forin:
Combining multicore and reconfigurable instruction set extensions. FPGA 2010: 33-36 - Chen Chen, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra:
Efficient FPGAs using nanoelectromechanical relays. FPGA 2010: 273-282 - Doris Chen, Deshanand P. Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz:
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs. FPGA 2010: 167-176 - Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, Kirill Minkovich, Bo Yuan, Yi Zou:
Accelerating Monte Carlo based SSTA using FPGA. FPGA 2010: 111-114 - Jason Cong, Kirill Minkovich:
LUT-based FPGA technology mapping for reliability (abstract only). FPGA 2010: 288 - Zefu Dai, Nick Ni, Jianwen Zhu:
A 1 cycle-per-byte XML parsing accelerator. FPGA 2010: 199-208 - Donglai Dai, Aniruddha S. Vaidya, Roy Saharoy, Seungjoon Park, Dongkook Park, Hariharan L. Thantry, Ralf Plate, Elmar Maas, Akhilesh Kumar, Mani Azimi:
FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only). FPGA 2010: 293 - Marc-André Daigneault, Jean-Pierre David:
Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only). FPGA 2010: 283 - Marcus Dutton, David C. Keezer:
An architecture for graphics processing in an FPGA (abstract only). FPGA 2010: 283 - Brahim Al Farisi, Karel Bruneel, Harald Devos, Dirk Stroobandt:
Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only). FPGA 2010: 287 - David L. Foster, Darrin M. Hanna:
Maximizing area-constrained partial fault tolerance in reconfigurable logic. FPGA 2010: 259-262 - Jan R. Frigo, Eric Y. Raby, Sean M. Brennan, Christophe Wolinski, Charles Wagner, François Charot, Edward Rosten, Vinod Kulathumani:
Energy efficient sensor node implementations. FPGA 2010: 37-40 - Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita:
Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only). FPGA 2010: 288 - Diana Göhringer, Michael Hübner, Michael Benz, Jürgen Becker:
A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only). FPGA 2010: 286 - Dharmendra P. Gupta, Paul Chow:
Acceleration of an analytical approach to collateralized debt obligation pricing. FPGA 2010: 103-106 - Y. Hamid, Martin Langhammer:
Multiplier architectures for FPGA double precision functions (abstract only). FPGA 2010: 287 - Kan Huang, Junlin Lu, Jiufeng Pang, Yansong Zheng, Hao Li, Dong Tong, Xu Cheng:
FPGA prototyping of an amba-based windows-compatible SoC. FPGA 2010: 13-22 - Chen Huang, Frank Vahid:
Server-side coprocessor updating for mobile devices with FPGAs. FPGA 2010: 125-134 - Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain:
Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only). FPGA 2010: 286 - Peter A. Jamieson, Kenneth B. Kent:
Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only). FPGA 2010: 288 - Zhanpeng Jin, Richard Neil Pittman, Alessandro Forin:
Reconfigurable custom floating-point instructions (abstract only). FPGA 2010: 287 - Jonathan M. Johnson, Michael J. Wirthlin:
Voter insertion algorithms for FPGA designs using triple modular redundancy. FPGA 2010: 249-258 - Sunwoo Kim, Won Woo Ro:
FPGA implementation of highly parallelized decoder logic for network coding (abstract only). FPGA 2010: 284 - Charles Eric LaForest, J. Gregory Steffan:
Efficient multi-ported memories for FPGAs. FPGA 2010: 41-50
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retrieved on 2024-05-26 04:42 CEST from data curated by the dblp team
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