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Publication search results
found 43 matches
- 2005
- Ali Akoglu, Sethuraman Panchanathan:
Application Specific Reconfigurable Architecture Design. ERSA 2005: 247-250 - Caaliph Andriamisaina, Catherine Dezan, Christophe Jégo, Bernard Pottier:
Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit. ERSA 2005: 263-266 - Donald W. Bouldin:
Enabling Killer Applications of Reconfigurable Systems: ERSA Keynote and Introduction. ERSA 2005: 7-16 - Chen Chang, John Wawrzynek, Pierre-Yves Droz, Robert W. Brodersen:
The Design And Application Of A High-End Reconfigurable Computing System. ERSA 2005: 129-136 - Robert P. Colwell:
Where Intel's Microprocessor Architecture is Going. ERSA 2005: 3-6 - Ryan A. DeVille, Ian A. Troxel, Alan D. George:
Performance Monitoring for Run-time Management of Reconfigurable Devices. ERSA 2005: 175-181 - Abdel Ejnioui, Ronald F. DeMara:
Area Reclamation Strategies and Metrics for SRAM-Based Reconfigurable Devices. ERSA 2005: 196-202 - Antonio Gentile, Salvatore Segreto, Filippo Sorbello, Giorgio Vassallo, Salvatore Vitabile, Vincenzo Vullo:
CliffoSor, an Innovative FPGA-based Architecture for Geometric Algebra. ERSA 2005: 211-217 - Wenrui Gong, Yan Meng, Gang Wang, Ryan Kastner, Timothy Sherwood:
Data Partitioning and Optimizations for Reconfigurable Architectures. ERSA 2005: 239-242 - Steven A. Guccione:
Microprocessors: The New LUT. ERSA 2005: 26-25 - Yuanqing Guo, Cornelis Hoede, Gerard J. M. Smit:
A Multi-Pattern Scheduling Algorithm. ERSA 2005: 276- - Frank Hannig, Jürgen Teich:
Output Serialization for FPGA-based and Coarse-grained Processor Arrays. ERSA 2005: 78-84 - Chuan He, Wei Zhao, Mi Lu:
FPGA-Based High-Order Finite Difference Algorithm for 2D Acoustic Wave Propagation Problems. ERSA 2005: 267-273 - Stefan Ihmor, Florian Dittmann:
Optimizing Interface Implementation Costs Using Runtime Reconfigurable Systems. ERSA 2005: 85-91 - Kimmo U. Järvinen, Matti Tommiska, Jorma Skyttä:
A Compact MD5 and SHA-1 Co-Implementation Utilizing Algorithm Similarities. ERSA 2005: 48-54 - Sungjoon Jung, Tag Gon Kim:
An Operation and Interconnection Sharing Algorithm for Partially Reconfigurable Architectures. ERSA 2005: 163-174 - Kenneth B. Kent, Zhao Yong, Jacqueline E. Rice, Troy Ronda:
Instance-Specific Versus Parameter-Specific Circuit Generation. ERSA 2005: 243-246 - Youngsoo Kim, Dongsoo Kim, Daesun Park, Sungjo Kim:
A Non-LIinear Function Generator Using BRM. ERSA 2005: 261-262 - Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo:
Flexible Core Reallocation for Virtex II Structures. ERSA 2005: 189-195 - Xuejun Liang, Jeffrey S. Vetter, Melissa C. Smith, Arthur S. Bland:
Balancing FPGA Resource Utilities. ERSA 2005: 156-162 - Shaoyu Liu, Gregory D. Peterson, Seong G. Kong:
A Hardware Implementation of a Dynamically Adjustable Block-based Neural Network. ERSA 2005: 203-210 - Wayne Luk, Sherif Yusuf, Morris Sloman, Geoffrey Brown, Emil C. Lupu, Naranker Dulay:
A Combined Hardware-Software Architecture for Network Flow. ERSA 2005: 149-155 - Jing Ma, Xinming Huang:
A SoPC Architecture of MIMO Sphere Decoder for Mobile Communications. ERSA 2005: 41-47 - Dror E. Maydan:
Configurable Processors and the Evolution of System-on-Chip Design. ERSA 2005: 37 - Wim J. C. Melis, Kieron Turkington, Alexander Whitton, Wayne Luk, Peter Y. K. Cheung, Paul Metzgen:
Cell Based Motion Estimators for Reconfigurable Platforms. ERSA 2005: 218-224 - Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe:
Reconfigurable 1-Bit Processor Array with Reduced Wirng Area. ERSA 2005: 225-234 - Otsebele E. Nare, Charles T. Johnson-Bey:
A Reconfigurable Antialiasing Filter Design Using Multi-Abstraction Design Exploration Approach. ERSA 2005: 235-238 - Jingzhao Ou, Viktor K. Prasanna:
Rapid Arithmetic Level Simulation Based Energy Estimation for Hardware/Software Co-Design Using FPGAs. ERSA 2005: 55-61 - Zexin Pan, Juanjo Noguera, B. Earl Wells:
Improved Microarchitecture Support for Dynamic Task Scheduling on Reconfigurable Architectures. ERSA 2005: 182-188 - Janak Porwal, Sachin B. Patkar:
Algorithms For Scheduling Of Data Transfer Across FPGAs In A Grid. ERSA 2005: 255-260
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