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Publication search results
found 79 matches
- 2006
- Mohamed Abbas, Makoto Ikeda, Kunihiro Asada:
Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow. DDECS 2006: 147-148 - Eero Aho, Jarno Vanne
, Timo D. Hämäläinen:
Parallel Memory Architecture for Arbitrary Stride Accesses. DDECS 2006: 65-70 - Eric Armengaud
:
Low Level Bus Traffic Replay for the Test and Debugging of Time-Triggered Communication Systems. DDECS 2006: 155-156 - Luz Balado, Emili Lupon
, L. García, Rosa Rodríguez-Montañés, Joan Figueras:
Lissajous Based Mixed-Signal Testing for N-Observable Signals. DDECS 2006: 125-130 - Manuel J. Barragan Asian, Diego Vázquez, Adoración Rueda
:
A Sinewave Analyzer for Mixed-Signal BIST Applications in a 0.35µm Technology. DDECS 2006: 119-124 - V. V. Belkin, S. G. Sharshunov:
ISA Based Functional Test Generation with Application to Self-Test of RISC Processors. DDECS 2006: 75-76 - Alfredo Benso
, Alberto Bosio, Stefano Di Carlo
, Giorgio Di Natale, Paolo Prinetto:
A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs. DDECS 2006: 157-158 - Paolo Bernardi
, Michelangelo Grosso
:
Test Considerations about the Structured ASIC Paradigm. DDECS 2006: 232-233 - Santosh Biswas, Siddhartha Mukhopadhyay, P. Patra, Dipankar Sarkar:
Concurrent Testing of Digital Circuits for Advanced Fault Models. DDECS 2006: 204-209 - György Bognár, Gyula Horváth, Zoltán Szucs, Vladimír Székely:
Die Attach Quality Testing by Fully Contact-less Measurement Method. DDECS 2006: 81-82 - Marco Bucci, Raimondo Luzzi:
A Leakage-based Random Bit Generator with On-line Fault Detection. DDECS 2006: 234-235 - Jirí Bucek, Róbert Lórencz
:
Comparing Subtraction-Free and Traditional AMI. DDECS 2006: 97-99 - Hsin-Chou Chi, Chia-Ming Wu, Sung-Tze Wu:
A Switch Supporting Circuit and Packet Switching for On-Chip Networks. DDECS 2006: 226-227 - Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. DDECS 2006: 256-261 - Piotr Dziurzanski, Wlodzimierz Bielecki, Konrad Trifunovic, M. Kleszczonek:
A System for Transforming an ANSI C Code with OpenMP Directives into a SystemC Description. DDECS 2006: 153-154 - Jochen Eisinger, Ilia Polian, Bernd Becker
, Alexander Metzner, Stephan Thesing, Reinhard Wilhelm:
Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis. DDECS 2006: 15-20 - Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet:
PE-ICE: Parallelized Encryption and Integrity Checking Engine. DDECS 2006: 143-144 - Félix Tobajas
, Roberto Esper-Chaín, Raúl Regidor, Octavio Santana, Roberto Sarmiento
:
A Low Power 2.5 Gbps 1: 32 Deserializer in SiGe BiCMOS Technology. DDECS 2006: 21-26 - José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira
, João Paulo Teixeira:
Probabilistic Testability Analysis and DFT Methods at RTL. DDECS 2006: 216-217 - André V. Fidalgo
, Gustavo R. Alves
, José M. Ferreira:
A Modified Debugging Infrastructure to Assist Real Time Fault Injection Campaigns. DDECS 2006: 174-179 - Petr Fiser, Hana Kubátová:
Multiple-Vector Column-Matching BIST Design Method. DDECS 2006: 268-273 - Zbysek Gajda:
A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming. DDECS 2006: 238-240 - Tomasz Garbolino
, Michal Kopec, Krzysztof Gucwa, Andrzej Hlawiczka:
Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor. DDECS 2006: 230-231 - Mario García-Valderas
, Marta Portela-García
, Celia López-Ongil
, Luis Entrena-Arrontes
:
An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories. DDECS 2006: 218-219 - Kristian Granhaug, Snorre Aunet:
Six Subthreshold Full Adder Cells Characterized in 90 nm CMOS Technology. DDECS 2006: 27-32 - F. Guerreiro, Jorge Semião
, A. Pierce, Marcelino B. Santos, Isabel C. Teixeira
, João Paulo Teixeira
:
Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage. DDECS 2006: 279-284 - Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian:
Minimal March-Based Fault Location Algorithm with Partial Diagnosis for all Static Faults in Random Access Memories. DDECS 2006: 262-267 - Shih-Chang Hsia, Wen-Ching Lee:
A New 6-bit Flash A/D Converter Using Novel Two-Step Structure. DDECS 2006: 103-107 - Jirí Jaros
, Václav Dvorák:
Evolutionary Design of OAB and AAB Communication Schedules for Networking Systems on Chips. DDECS 2006: 222-223 - Yves Joannon, Vincent Beroulle, Rami Khouri, Chantal Robach, Smail Tedjini
, Jean-Louis Carbonéro:
Behavioral Modeling of WCDMA Transceiver with VHDL-AMS Language. DDECS 2006: 113-118
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