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Publication search results
found 21 matches
- 2018
- Thomas Haywood Dadzie, Jihye Kim, Hyunok Oh:
Secure non-volatile memory with scratch pad memory using dual encryption mode: work-in-progress. CODES+ISSS 2018: 6 - Yejia Di, Liang Shi, Congming Gao, Qiao Li, Chun Jason Xue:
Revisiting wear leveling design on compression applied 3D NAND flash memory: work-in-progress. CODES+ISSS 2018: 10 - Jian Fang, Jianyu Chen, Zaid Al-Ars, H. Peter Hofstee, Jan Hidders:
A high-bandwidth snappy decompressor in reconfigurable logic: work-in-progress. CODES+ISSS 2018: 16 - Sena Hounsinou, Aishwarya Vasu, Harini Ramaprasad:
Hardware implementation of a multi-mode-aware mixed-criticality scheduler: work-in-progress. CODES+ISSS 2018: 8 - Wei Jiang, Liugen Xiu, Jinyu Zhan, Ke Jiang:
Co-design of security-critical real-time systems to prevent fault injection attacks: work-in-progress. CODES+ISSS 2018: 9 - Lihui Jin, Chao Wang, Lei Gong, Chongchong Xu, Yahui Hu, Luchao Tan, Xuehai Zhou:
Furion: alleviating overheads for deep learning framework on single machine (work-in-progress). CODES+ISSS 2018: 14 - Mengquan Li, Weichen Liu, Lei Yang, Yiyuan Xie, Yaoyao Ye, Nan Guan:
Communication optimization for thermal reliable optical network-on-chip: work-in-progress. CODES+ISSS 2018: 3 - Markus Miettinen, Ahmad-Reza Sadeghi:
Internet of things or threats?: on building trust in IoT (keynote). CODES+ISSS 2018: 1 - Kai Neubauer, Christian Haubelt, Philipp Wanko, Torsten Schaub:
On leveraging approximations for exact system-level design space exploration: work-in-progress. CODES+ISSS 2018: 15 - Manuele Rusci, Alessandro Capotondi, Francesco Conti, Luca Benini:
Quantized NNs as the definitive solution for inference on low-power ARM MCUs?: work-in-progress. CODES+ISSS 2018: 12 - Selma Saidi, Sebastian Steinhorst, Arne Hamann, Dirk Ziegenbein, Marko Wolf:
Future automotive systems design: research challenges and opportunities: special session. CODES+ISSS 2018: 2 - Minjun Seo, Roman Lysecky:
Runtime requirements monitoring for state-based hardware: work-in-progress. CODES+ISSS 2018: 7 - Stefano Spellini, Michele Lora, Sudipta Chattopadhyay, Franco Fummi:
Introducing assume-guarantee contracts for verifying robotic applications: work-in-progress. CODES+ISSS 2018: 4 - Hongfei Wang, Jianwen Li, Kun He, Wenjie Cai:
Hierarchical ensemble learning for resource-aware FPGA computing: work-in-progress. CODES+ISSS 2018: 18 - Xuan Wang, Chao Wang, Xuehai Zhou:
WinoNN: optimising FPGA-based neural network accelerators using fast winograd algorithm (work-in-progress). CODES+ISSS 2018: 17 - Taimour Wehbe, Vincent John Mooney, David C. Keezer:
A chip-level security framework for assessing sensor data integrity: work-in-progress. CODES+ISSS 2018: 20 - Jan Henrik Weinstock, Robert Lajos Bücs, Florian Walbroel, Rainer Leupers, Gerd Ascheid:
AMVP - a high performance virtual platform using parallel systemC for multicore ARM architectures: work-in-progress. CODES+ISSS 2018: 13 - Kang Yang, Rui Wang, Yu Jiang, Chenxia Luo, Yong Guan, Xiaojuan Li, Zhiping Shi:
Enhanced resilient sensor attack detection using fusion interval and measurement history. CODES+ISSS 2018: 19 - Jinyu Zhan, Junhuan Yang, Wei Jiang, Yixin Li:
Dynamic data management for automotive ECUs with hybrid RAM-NVM memory: work-in-progress. CODES+ISSS 2018: 5 - Xue-Yang Zhu:
Equivalence of transformations of synchronous data flow graphs: work-in-progress. CODES+ISSS 2018: 11 - Aviral Shrivastava, Sudeep Pasricha:
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2018, part of ESWEEK 2018, Torino, Italy, September 30 - October 5, 2018. IEEE / ACM 2018, ISBN 978-1-5386-5562-7 [contents]
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