- Wing Ning Li, Sartaj Sahni:
Pull up transistor folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(5): 512-521 (1990) - Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai:
Hybrid routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2): 151-157 (1990) - Bill Lin, A. Richard Newton:
A circuit disassembly technique for synthesizing symbolic layouts from mask descriptions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(9): 959-969 (1990) - Nam Ling, Magdy A. Bayoumi:
Systolic temporal arithmetic: a new formalism for specification and verification of systolic arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8): 804-820 (1990) - W. T. Liou, Jimmy J. M. Tan, Richard C. T. Lee:
Minimum rectangular partition problem for simple rectilinear polygons. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7): 720-733 (1990) - Peter Lloyd, Heinz K. Dirks, E. James Prendergast, Kishore Singhal:
Technology CAD for competitive products. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(11): 1209-1216 (1990) - Paolo Lugli:
The Monte Carlo method for semiconductor device and process modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(11): 1164-1176 (1990) - Fadi Maamari, Janusz Rajski:
A method of fault simulation based on stem regions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2): 212-220 (1990) - Clifford D. Maldonado, Ross A. Williams:
A transient analytical model for predicting the redistribution of injected interstitials. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8): 846-855 (1990) - Weiwei Mao, Michael D. Ciletti:
DYTEST: a self-learning algorithm using dynamic testability measures to accelerate test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8): 893-898 (1990) - David Marple, Michiel Smulders, Henk Hegen:
Tailor: a layout system based on trapezoidal corner stitching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(1): 66-90 (1990) - Robert L. Maziasz, John P. Hayes:
Layout optimization of static CMOS functional cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7): 708-719 (1990) - Michael C. McFarland, Thaddeus J. Kowalski:
Incorporating bottom-up design into hardware synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(9): 938-950 (1990) - Kurt Mehlhorn, Stefan Näher:
A faster compaction algorithm with automatic jog insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2): 158-166 (1990) - Kurt Mehlhorn, Wolfgang Rülling:
Compaction on the torus [VLSI layout]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4): 389-397 (1990) - Paul Molitor
:
Constrained via minimization for systolic arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(5): 537-542 (1990) - Brian T. Murray, John P. Hayes:
Hierarchical test generation using precomputed tests for modules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(6): 594-603 (1990) - Farid N. Najm, Richard Burch, Ping Yang, Ibrahim N. Hajj:
Probabilistic simulation for reliability analysis of CMOS VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4): 439-450 (1990) - Farid N. Najm, Ibrahim N. Hajj:
The complexity of fault detection in MOS VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(9): 995-1001 (1990) - Arokia Nathan, Henry Baltes, Walter Allegretto:
Review of physical models for numerical simulation of semiconductor microsensors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(11): 1198-1208 (1990) - Patrick Odent, Luc J. M. Claesen, Hugo De Man:
Acceleration of relaxation-based circuit simulation using a multiprocessor system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(10): 1063-1072 (1990) - Makiko Okumura, Tsutomu Sugawara, Hiroshi Tanimoto:
An efficient small signal frequency analysis method of nonlinear circuits with two frequency excitations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 225-235 (1990) - Michael D. Osterman, Michael G. Pecht
:
Placement for reliability and routability of convectively cooled PWBs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7): 734-744 (1990) - Christos A. Papachristou, Anil L. Pandya:
A design scheme for PLA-based control tables with reduced area and time-delay cost. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(5): 453-472 (1990) - Anthony E. Parker, David J. Skellern:
An improved FET model for computer simulators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(5): 551-553 (1990) - Matthias Passlack, Manfred Uhle, Horst Elschner:
Analysis of propagation delays in high-speed VLSI circuits using a distributed line model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8): 821-826 (1990) - Srinivas Patil, Prithviraj Banerjee:
A parallel branch and bound algorithm for test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 313-322 (1990) - Wim De Pauw, Ludo Weyten
:
Multiple storage adaptive multi-trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 248-252 (1990) - Lawrence T. Pillage, Ronald A. Rohrer:
Asymptotic waveform evaluation for timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4): 352-366 (1990) - Ernst Rank
, Ulrich Weinert:
A simulation system for diffusive oxidation of silicon: a two-dimensional finite element approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(5): 543-550 (1990)