- Francis Depuydt, Werner Geurts, Gert Goossens, Hugo De Man:
Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization. EDAC-ETC-EUROASIC 1994: 490-494 - Muhammad K. Dhodhi, Imtiaz Ahmad, C. Y. Roger Chen:
Synthesis of Application-Specific Multiprocessor Systems. EDAC-ETC-EUROASIC 1994: 671 - Rob van Dongen, Vincent Rikkink:
Advanced Analog Circuit Design on a Digital Sea-of-Gates Array. EDAC-ETC-EUROASIC 1994: 70-74 - Stéphane Donnay, Koen Swings, Georges G. E. Gielen, Willy M. C. Sansen, Wim Kruiskamp, Domine Leenaerts:
A Methodology for Analog Design Automation in Mixed-Signal ASICs. EDAC-ETC-EUROASIC 1994: 530-534 - Jean-Claude Dufourd, Jean-François Naviner:
An Optimizable Model for Process Independent Symbolic Design. EDAC-ETC-EUROASIC 1994: 660 - D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. EDAC-ETC-EUROASIC 1994: 518-523 - Martyn Edwards, John Forrest:
A Development Environment for the Cosynthesis of Embedded Software/Hardware Systems. EDAC-ETC-EUROASIC 1994: 469-473 - Henrik Esbensen, Pinaki Mazumder:
A Genetic Algorithm for the Steiner Problem in a Graph. EDAC-ETC-EUROASIC 1994: 402-406 - Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò:
Modeling of Broken Connections Faults in CMOS ICs. EDAC-ETC-EUROASIC 1994: 159-164 - Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre:
Automatic Synthesis of BISTed Data Paths From High Level Specification. EDAC-ETC-EUROASIC 1994: 591-598 - Frank H. M. Franssen, Lode Nachtergaele, Hans Samsom, Francky Catthoor, Hugo De Man:
Control flow optimization for fast system simulation and storage minimization. EDAC-ETC-EUROASIC 1994: 20-24 - Jürgen Frößl, Thomas Kropf:
A New Model to Uniformly Represent the Function and Timing of MOS Circuits and its Application to VHDL Simulation. EDAC-ETC-EUROASIC 1994: 343-348 - Franco Fummi, Donatella Sciuto, Micaela Serra:
A Functional Approach to Delay Faults Test Generation for Sequential Circuits. EDAC-ETC-EUROASIC 1994: 51-57 - Silvano Gai, Pier Luca Montessoro, Matteo Sonza Reorda:
TORSIM: An Efficient Fault Simulator for Synchronous Sequential Circuits. EDAC-ETC-EUROASIC 1994: 46-50 - Daniel Gajski, Frank Vahid, Sanjiv Narayan:
A System-Design Methodology: Executable-Specification Refinement. EDAC-ETC-EUROASIC 1994: 458-463 - Dorine Gevaert, Jozef Vanneuville, Jiri Nedved, Jan Sevenhans:
Switched Current Sigma-Delta A/D Converter for a CMOS Subscriber Line Analog Front End. EDAC-ETC-EUROASIC 1994: 75-79 - Lakshmikanth Ghatraju, Mostafa I. H. Abd-El-Barr, Carl McCrosky:
High-Level Synthesis of Digital Circuits by Finding Fixpoints. EDAC-ETC-EUROASIC 1994: 94-98 - Douglas M. Grant, Jef L. van Meerbergen, Paul E. R. Lippens:
Optimization of Address Generator Hardware. EDAC-ETC-EUROASIC 1994: 325-329 - Alain Greiner, Luis Lucas, Franck Wajsbürt, Laurent Winckel:
Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library. EDAC-ETC-EUROASIC 1994: 9-13 - Oliver F. Haberl, Thomas Kropf:
Self Testable Boards with Standard IEEE 1149.5 Module Test and Maintenance (MTM) Bus Interface. EDAC-ETC-EUROASIC 1994: 220-225 - Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi:
Symbolic Algorithms to Calculate Steady-State Probabilities of a Finite State Machine. EDAC-ETC-EUROASIC 1994: 214-218 - Ralf Hahn, Rolf Krieger, Bernd Becker:
A Hierarchical Approach to Fault Collapsing. EDAC-ETC-EUROASIC 1994: 171-176 - Ian G. Harris, Alex Orailoglu:
Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST. EDAC-ETC-EUROASIC 1994: 119-123 - Johannes Helbig, Peter Kelb:
An OBDD-Representation of Statecharts. EDAC-ETC-EUROASIC 1994: 142-149 - Sybille Hellebrand, Hans-Joachim Wunderlich:
Synthesis of Self-Testable Controllers. EDAC-ETC-EUROASIC 1994: 580-585 - Mokhtar Hirech, Olivier Florent, Alain Greiner, El Housseine Rejouan:
A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking. EDAC-ETC-EUROASIC 1994: 668 - Nancy D. Holmes, Daniel Gajski:
An Algorithm for Generation of Behavioral Shape Functions. EDAC-ETC-EUROASIC 1994: 314-318 - Shan-Hsi Huang, Jan M. Rabaey:
Maximizing the Throughput of High Performance DSP Applications Using Behavioral Transformations. EDAC-ETC-EUROASIC 1994: 25-30 - Ed P. Huijbregts, Jos T. J. van Eijndhoven, Jochen A. G. Jess:
On Design Rule Correct Maze Routing. EDAC-ETC-EUROASIC 1994: 407-411 - Makoto Ikeda, Kunihiro Asada:
A Reduced-swing Data Transmission Scheme for Resistive Bus Lines in VSLIs. EDAC-ETC-EUROASIC 1994: 546-550