- Sai Prashanth Muralidhara, Mahmut T. Kandemir:
Communication Based Proactive Link Power Management. Trans. High Perform. Embed. Archit. Compil. 4: 135-154 (2011) - William George Osborne, Wayne Luk, José Gabriel F. Coutinho, Oskar Mencer:
Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation. Trans. High Perform. Embed. Archit. Compil. 4: 354-369 (2011) - William Plishker, Nimish Sane, Mary Kiemb, Shuvra S. Bhattacharyya:
Heterogeneous Design in Functional DIF. Trans. High Perform. Embed. Archit. Compil. 4: 391-408 (2011) - Markus Rullmann, Renate Merker:
A Cost Model for Partial Dynamic Reconfiguration. Trans. High Perform. Embed. Archit. Compil. 4: 370-390 (2011) - Tarik Saidani, Lionel Lacassagne, Joel Falcou, Claude Tadonki, Samir Bouaziz:
Parallelization Schemes for Memory Optimization on the Cell Processor: A Case Study on the Harris Corner Detector. Trans. High Perform. Embed. Archit. Compil. 3: 177-200 (2011) - Subhradyuti Sarkar, Dean M. Tullsen
:
Data Layout for Cache Performance on a Multithreaded Architecture. Trans. High Perform. Embed. Archit. Compil. 3: 43-68 (2011) - Yiannakis Sazeides, Andreas Moustakas, Kypros Constantinides, Marios Kleanthous:
Improving Branch Prediction by Considering Affectors and Affectees Correlations. Trans. High Perform. Embed. Archit. Compil. 3: 69-88 (2011) - Frederik Vandeputte, Lieven Eeckhout:
Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces. Trans. High Perform. Embed. Archit. Compil. 4: 21-41 (2011) - Frederik Vandeputte, Lieven Eeckhout:
Finding Extreme Behaviors in Microprocessor Workloads. Trans. High Perform. Embed. Archit. Compil. 4: 155-174 (2011) - Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
:
A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture. Trans. High Perform. Embed. Archit. Compil. 4: 215-233 (2011) - M. M. Waliullah:
Efficient Partial Roll-Backing Mechanism for Transactional Memory Systems. Trans. High Perform. Embed. Archit. Compil. 3: 256-274 (2011) - Adam Welc, Bratin Saha:
Software Transactional Memory Validation - Time and Space Considerations. Trans. High Perform. Embed. Archit. Compil. 4: 254-273 (2011) - Nan Wu, Qianming Yang, Mei Wen, Yi He, Ju Ren, Maolin Guan, Chunyuan Zhang:
Tiled Multi-Core Stream Architecture. Trans. High Perform. Embed. Archit. Compil. 4: 274-293 (2011) - Nan Yuan, Lei Yu, Dongrui Fan:
An Efficient and Flexible Task Management for Many Cores. Trans. High Perform. Embed. Archit. Compil. 4: 294-310 (2011) - Per Stenström:
Transactions on High-Performance Embedded Architectures and Compilers III. Lecture Notes in Computer Science 6590, Springer 2011, ISBN 978-3-642-19447-4 [contents] - Per Stenström:
Transactions on High-Performance Embedded Architectures and Compilers IV. Lecture Notes in Computer Science 6760, Springer 2011, ISBN 978-3-642-24567-1 [contents] - 2009
- Aneesh Aggarwal:
Complexity Effective Bypass Networks. Trans. High Perform. Embed. Archit. Compil. 2: 201-221 (2009) - Minwook Ahn, Yunheung Paek:
Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers. Trans. High Perform. Embed. Archit. Compil. 2: 149-172 (2009) - Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson:
Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems. Trans. High Perform. Embed. Archit. Compil. 2: 65-84 (2009) - Arquimedes Canedo, Ben A. Abderazek
, Masahiro Sowa:
Compiler Support for Code Size Reduction Using a Queue-Based Processor. Trans. High Perform. Embed. Archit. Compil. 2: 269-285 (2009) - Dominique Chanet, Javier Cabezas, Enric Morancho, Nacho Navarro, Koen De Bosschere:
Linux Kernel Compaction through Cold Code Swapping. Trans. High Perform. Embed. Archit. Compil. 2: 173-200 (2009) - Woojin Choi, Seok-Jun Park, Michel Dubois:
Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors. Trans. High Perform. Embed. Archit. Compil. 2: 107-127 (2009) - Amit Golander, Shlomo Weiss:
Reexecution and Selective Reuse in Checkpoint Processors. Trans. High Perform. Embed. Archit. Compil. 2: 242-268 (2009) - Chunling Hu, Daniel A. Jiménez, Ulrich Kremer:
Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization. Trans. High Perform. Embed. Archit. Compil. 2: 85-104 (2009) - Khaled Z. Ibrahim, Smaïl Niar:
Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC. Trans. High Perform. Embed. Archit. Compil. 2: 286-306 (2009) - Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras:
Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches. Trans. High Perform. Embed. Archit. Compil. 2: 4-22 (2009) - Simon Kluyskens, Lieven Eeckhout:
Branch Predictor Warmup for Sampled Simulation through Branch History Matching. Trans. High Perform. Embed. Archit. Compil. 2: 45-64 (2009) - Patrick Mahoney, Yvon Savaria, Guy Bois, Patrice Plante:
Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories. Trans. High Perform. Embed. Archit. Compil. 2: 307-325 (2009) - Vijay Nagarajan, Rajiv Gupta
, Arvind Krishnaswamy:
Compiler-Assisted Memory Encryption for Embedded Processors. Trans. High Perform. Embed. Archit. Compil. 2: 23-44 (2009) - Christine Rochange, Pascal Sainrat:
A Context-Parameterized Model for Static Analysis of Execution Times. Trans. High Perform. Embed. Archit. Compil. 2: 222-241 (2009)