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@article{DBLP:journals/tvlsi/AudetC97,
  author       = {Yves Audet and
                  Glenn H. Chapman},
  title        = {Yield improvement of a large area magnetic field sensor array using
                  redundancy schemes},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {1},
  pages        = {28--33},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.555984},
  doi          = {10.1109/92.555984},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/AudetC97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/BajwaHKGNSSS97,
  author       = {Raminder Singh Bajwa and
                  Mitsuru Hiraki and
                  Hirotsugu Kojima and
                  Douglas J. Gorny and
                  Ken{-}ichi Nitta and
                  Avadhani Shridhar and
                  Koichi Seki and
                  Katsuro Sasaki},
  title        = {Instruction buffering to reduce power in processors for signal processing},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {4},
  pages        = {417--424},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.645068},
  doi          = {10.1109/92.645068},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/BajwaHKGNSSS97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/BergamaschiRNT97,
  author       = {Reinaldo A. Bergamaschi and
                  Salil Raje and
                  Indira Nair and
                  Louise Trevillyan},
  title        = {Control-flow versus data-flow-based scheduling: combining both approaches
                  in an adaptive scheduling system},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {1},
  pages        = {82--100},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.555989},
  doi          = {10.1109/92.555989},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/BergamaschiRNT97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/BolioloBMR97,
  author       = {Alessandro Bogliolo and
                  Luca Benini and
                  Giovanni De Micheli and
                  Bruno Ricc{\`{o}}},
  title        = {Gate-level power and current simulation of {CMOS} integrated circuits},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {4},
  pages        = {473--488},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.645074},
  doi          = {10.1109/92.645074},
  timestamp    = {Mon, 15 Jun 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/BolioloBMR97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/BugejaY97,
  author       = {Alex R. Bugeja and
                  W. Yang},
  title        = {A reconfigurable {VLSI} coprocessing system for the block matching
                  algorithm},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {3},
  pages        = {329--337},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.609876},
  doi          = {10.1109/92.609876},
  timestamp    = {Fri, 08 Apr 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/BugejaY97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ChangP97,
  author       = {Jui{-}Ming Chang and
                  Massoud Pedram},
  title        = {Energy minimization using multiple supply voltages},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {4},
  pages        = {436--443},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.645070},
  doi          = {10.1109/92.645070},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChangP97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ChaudhuriBW97,
  author       = {Samit Chaudhuri and
                  S. A. Blthye and
                  Robert A. Walker},
  title        = {A solution methodology for exact design space exploration in a three-dimensional
                  design space},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {1},
  pages        = {69--81},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.555988},
  doi          = {10.1109/92.555988},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChaudhuriBW97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ChouSA97,
  author       = {Richard M. Chou and
                  Kewal K. Saluja and
                  Vishwani D. Agrawal},
  title        = {Scheduling tests for {VLSI} systems under power constraints},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {2},
  pages        = {175--185},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.585217},
  doi          = {10.1109/92.585217},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChouSA97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ChungH97,
  author       = {Pi{-}Yu Chung and
                  Ibrahim N. Hajj},
  title        = {Diagnosis and correction of multiple logic design errors in digital
                  circuits},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {2},
  pages        = {233--237},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.585227},
  doi          = {10.1109/92.585227},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChungH97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/Coudert97,
  author       = {Olivier Coudert},
  title        = {Gate sizing for constrained delay/power/area optimization},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {4},
  pages        = {465--472},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.645073},
  doi          = {10.1109/92.645073},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/Coudert97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/DaveauMIJ97,
  author       = {Jean{-}Marc Daveau and
                  Gilberto Fernandes Marchioro and
                  Tarek Ben Ismail and
                  Ahmed Amine Jerraya},
  title        = {Protocol selection and interface generation for {HW-SW} codesign},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {1},
  pages        = {136--144},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.555993},
  doi          = {10.1109/92.555993},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/DaveauMIJ97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/DigeleLK97,
  author       = {G. Digele and
                  S. Lindenkreuz and
                  E. Kasper},
  title        = {Fully coupled dynamic electro-thermal simulation},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {3},
  pages        = {250--257},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.609867},
  doi          = {10.1109/92.609867},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/DigeleLK97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/DuttH97,
  author       = {Shantanu Dutt and
                  Fran Hanchek},
  title        = {{REMOD:} a new methodology for designing fault-tolerant arithmetic
                  circuits},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {1},
  pages        = {34--56},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.555985},
  doi          = {10.1109/92.555985},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/DuttH97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/EiseleBSM97,
  author       = {M. Eisele and
                  J{\"{o}}rg Berthold and
                  Doris Schmitt{-}Landsiedel and
                  R. Mahnkopf},
  title        = {The impact of intra-die device parameter variations on path delays
                  and on the design for yield of low voltage digital circuits},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {4},
  pages        = {360--368},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.645062},
  doi          = {10.1109/92.645062},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/EiseleBSM97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/FisherDRF97,
  author       = {Godi Fischer and
                  James C. Daly and
                  Conrad W. Recksiek and
                  Kevin D. Friedland},
  title        = {A programmable temperature monitoring device for tagging small fish:
                  a prototype chip development},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {4},
  pages        = {401--407},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.645066},
  doi          = {10.1109/92.645066},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/FisherDRF97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/GutnikC97,
  author       = {Vadim Gutnik and
                  Anantha P. Chandrakasan},
  title        = {Embedded power supply for low-power {DSP}},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {4},
  pages        = {425--435},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.645069},
  doi          = {10.1109/92.645069},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/GutnikC97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/HuangB97,
  author       = {Qiuting Huang and
                  Philipp Basedau},
  title        = {Design considerations for high-frequency crystal oscillators digitally
                  trimmable to sub-ppm accuracy},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {4},
  pages        = {408--416},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.645067},
  doi          = {10.1109/92.645067},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/HuangB97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/HuangW97,
  author       = {Steve C.{-}Y. Huang and
                  Wayne H. Wolf},
  title        = {Unifiable scheduling and allocation for minimizing system cycle time},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {2},
  pages        = {197--210},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.585222},
  doi          = {10.1109/92.585222},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/HuangW97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/JainL97,
  author       = {Vijay K. Jain and
                  Lei Lin},
  title        = {Complex-argument universal nonlinear cell for rapid prototyping},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {1},
  pages        = {15--27},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.555983},
  doi          = {10.1109/92.555983},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/JainL97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/JeongB97,
  author       = {Yongjin Jeong and
                  Wayne P. Burleson},
  title        = {{VLSI} array algorithms and architectures for {RSA} modular multiplication},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {2},
  pages        = {211--217},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.585224},
  doi          = {10.1109/92.585224},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/JeongB97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/JerrayaG97,
  author       = {Ahmed Amine Jerraya and
                  Gert Goossens},
  title        = {Guest Editorial Introduction to the Special Issue on the Eighth {IEEE}
                  International Symposium on System Synthesis},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {1},
  pages        = {57--58},
  year         = {1997},
  url          = {https://doi.org/10.1109/TVLSI.1997.555986},
  doi          = {10.1109/TVLSI.1997.555986},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/JerrayaG97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/KantawalaT97,
  author       = {Kamal Kantawala and
                  Dali L. Tao},
  title        = {Design, analysis, and evaluation of concurrent checking sorting networks},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {3},
  pages        = {338--343},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.609877},
  doi          = {10.1109/92.609877},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/KantawalaT97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/KorenK97,
  author       = {Zahava Koren and
                  Israel Koren},
  title        = {On the effect of floorplanning on the yield of large area integrated
                  circuits},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {1},
  pages        = {3--14},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.555982},
  doi          = {10.1109/92.555982},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/KorenK97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/KrishnamurthyC97,
  author       = {Ram K. Krishnamurthy and
                  L. Richard Carley},
  title        = {Exploring the design space of mixed swing quadrail for low-power digital
                  circuits},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {4},
  pages        = {388--400},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.645065},
  doi          = {10.1109/92.645065},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/KrishnamurthyC97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LaiW97,
  author       = {Yen{-}Tai Lai and
                  Ping{-}Tsung Wang},
  title        = {Hierarchical interconnection structures for field programmable gate
                  arrays},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {2},
  pages        = {186--196},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.585219},
  doi          = {10.1109/92.585219},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LaiW97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LeeTMF97,
  author       = {Mike Tien{-}Chien Lee and
                  Vivek Tiwari and
                  Sharad Malik and
                  Masahiro Fujita},
  title        = {Power analysis and minimization techniques for embedded {DSP} software},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {1},
  pages        = {123--135},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.555992},
  doi          = {10.1109/92.555992},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LeeTMF97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LeupersM97,
  author       = {Rainer Leupers and
                  Peter Marwedel},
  title        = {Time-constrained code compaction for DSPs},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {1},
  pages        = {112--122},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.555991},
  doi          = {10.1109/92.555991},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LeupersM97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LimS97,
  author       = {Yong Je Lim and
                  Mani Soma},
  title        = {Statistical estimation of delay-dependent switching activities in
                  embedded {CMOS} combinational circuits},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {3},
  pages        = {309--319},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.609874},
  doi          = {10.1109/92.609874},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LimS97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LipmanY97,
  author       = {Aaron Lipman and
                  Woodward Yang},
  title        = {{VLSI} hardware for example-based learning},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {3},
  pages        = {320--328},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.609875},
  doi          = {10.1109/92.609875},
  timestamp    = {Fri, 21 May 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LipmanY97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/MaLPCKKP97,
  author       = {Jun Ma and
                  Han{-}Bin Liang and
                  R. A. Pryor and
                  Sunny Cheng and
                  M. H. Kaneshiro and
                  C. S. Kyono and
                  Ken Papworth},
  title        = {Graded-channel {MOSFET} {(GCMOSFET)} for high performance, low voltage
                  {DSP} applications},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {4},
  pages        = {352--359},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.645061},
  doi          = {10.1109/92.645061},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/MaLPCKKP97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/NekiliBS97,
  author       = {Mohamed Nekili and
                  Guy Bois and
                  Yvon Savaria},
  title        = {Pipelined H-trees for high-speed clocking of large integrated systems
                  in presence of process variations},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {2},
  pages        = {161--174},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.585214},
  doi          = {10.1109/92.585214},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/NekiliBS97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/NgA97,
  author       = {Hiok{-}Tiaq Ng and
                  David J. Allstot},
  title        = {{CMOS} current steering logic for low-voltage mixed-signal integrated
                  circuits},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {3},
  pages        = {301--308},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.609873},
  doi          = {10.1109/92.609873},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/NgA97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/RaffoSMGB97,
  author       = {Luigi Raffo and
                  Silvio P. Sabatini and
                  Mauro Mantelli and
                  Alessandro De Gloria and
                  Giacomo M. Bisio},
  title        = {Design of an {ASIP} architecture for low-level visual elaborations},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {1},
  pages        = {145--153},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.555994},
  doi          = {10.1109/92.555994},
  timestamp    = {Thu, 18 Feb 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/RaffoSMGB97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/SabryBAV97,
  author       = {M.{-}N. Sabry and
                  A. Bontemps and
                  V. Aubert and
                  R. Vahrmann},
  title        = {Realistic and efficient simulation of electro-thermal effects in {VLSI}
                  circuits},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {3},
  pages        = {283--289},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.609871},
  doi          = {10.1109/92.609871},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/SabryBAV97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/SchaumontVBM97,
  author       = {Patrick Schaumont and
                  Bart Vanthournout and
                  Ivo Bolsens and
                  Hugo De Man},
  title        = {Synthesis of pipelined {DSP} accelerators with dynamic scheduling},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {1},
  pages        = {59--68},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.555987},
  doi          = {10.1109/92.555987},
  timestamp    = {Mon, 15 Jun 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/SchaumontVBM97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/SchmitT97,
  author       = {Herman Schmit and
                  Donald E. Thomas},
  title        = {Synthesis of application-specific memory designs},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {1},
  pages        = {101--111},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.555990},
  doi          = {10.1109/92.555990},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/SchmitT97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/StanB97,
  author       = {Mircea R. Stan and
                  Wayne P. Burleson},
  title        = {Low-power encodings for global communication in {CMOS} {VLSI}},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {4},
  pages        = {444--455},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.645071},
  doi          = {10.1109/92.645071},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/StanB97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/SzekelyMKR97,
  author       = {Vladim{\'{\i}}r Sz{\'{e}}kely and
                  Cs. M{\'{a}}rta and
                  Zsolt Koh{\'{a}}ri and
                  M{\'{a}}rta Rencz},
  title        = {{CMOS} sensors for on-line thermal monitoring of {VLSI} circuits},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {3},
  pages        = {270--276},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.609869},
  doi          = {10.1109/92.609869},
  timestamp    = {Fri, 30 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/SzekelyMKR97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/SzekelyPPCHR97,
  author       = {Vladim{\'{\i}}r Sz{\'{e}}kely and
                  Andr{\'{a}}s Poppe and
                  Andras Pahi and
                  Alpar Csendes and
                  G. Hajas and
                  M{\'{a}}rta Rencz},
  title        = {Electro-thermal and logi-thermal simulation of {VLSI} designs},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {3},
  pages        = {258--269},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.609868},
  doi          = {10.1109/92.609868},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/SzekelyPPCHR97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/TangDM97,
  author       = {Xinghai Tang and
                  Vivek De and
                  James D. Meindl},
  title        = {Intrinsic {MOSFET} parameter fluctuations due to random dopant placement},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {4},
  pages        = {369--376},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.645063},
  doi          = {10.1109/92.645063},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/TangDM97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/TewksburyC97,
  author       = {Stuart K. Tewksbury and
                  Glenn H. Chapman},
  title        = {Guest Editorial Foreword to the Special Section on WSI'95},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {1},
  pages        = {1--2},
  year         = {1997},
  url          = {https://doi.org/10.1109/TVLSI.1997.555981},
  doi          = {10.1109/TVLSI.1997.555981},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/TewksburyC97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/TienLGTM97,
  author       = {Chien{-}Kuo V. Tien and
                  Kelvin Lewis and
                  Hans J. Greub and
                  Tom Tsen and
                  John F. McDonald},
  title        = {Design of a 32 b monolithic microprocessor based on GaAs {HMESFET}
                  technology},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {2},
  pages        = {238--243},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.585228},
  doi          = {10.1109/92.585228},
  timestamp    = {Fri, 01 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/TienLGTM97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/Tuagi97,
  author       = {A. Tuagi},
  title        = {Entropic bounds on {FSM} switching},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {4},
  pages        = {456--464},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.645072},
  doi          = {10.1109/92.645072},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/Tuagi97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/Vemuru97,
  author       = {S. R. Vemuru},
  title        = {Effects of simultaneous switching noise on the tapered buffer design},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {3},
  pages        = {290--300},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.609872},
  doi          = {10.1109/92.609872},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/Vemuru97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/Wolf97,
  author       = {Wayne Hendrix Wolf},
  title        = {An architectural co-synthesis algorithm for distributed, embedded
                  computing systems},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {2},
  pages        = {218--229},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.585225},
  doi          = {10.1109/92.585225},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/Wolf97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/WunscheCSW97,
  author       = {S. W{\"{u}}nsche and
                  C. Clauss and
                  Peter Schwarz and
                  Frank Winkler},
  title        = {Electro-thermal circuit simulation using simulator coupling},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {3},
  pages        = {277--282},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.609870},
  doi          = {10.1109/92.609870},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/WunscheCSW97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/YamauchiIAM97,
  author       = {Hiroyuki Yamauchi and
                  Toru Iwata and
                  Hironori Akamatsu and
                  Akira Matsuzawa},
  title        = {A 0.5 {V} single power supply operated high-speed boosted and offset-grounded
                  data storage {(BOGS)} {SRAM} cell architecture},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {4},
  pages        = {377--387},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.645064},
  doi          = {10.1109/92.645064},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/YamauchiIAM97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ZhangE97,
  author       = {David Zhang and
                  Mohamed I. Elmasry},
  title        = {{VLSI} compressor design with applications to digital neural networks},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {5},
  number       = {2},
  pages        = {230--233},
  year         = {1997},
  url          = {https://doi.org/10.1109/92.585226},
  doi          = {10.1109/92.585226},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ZhangE97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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