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@article{DBLP:journals/tvlsi/0004YLFLW18,
author = {Zhao Zhang and
Jincheng Yang and
Liyuan Liu and
Peng Feng and
Jian Liu and
Nanjian Wu},
title = {A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid
Digital {PLL} With Loop Bandwidth-Tracking Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {933--944},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2797280},
doi = {10.1109/TVLSI.2018.2797280},
timestamp = {Mon, 18 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/0004YLFLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/0004ZSCHWQZCXM18,
author = {Jing Guo and
Lei Zhu and
Yu Sun and
Huiliang Cao and
Hai Huang and
Tianqi Wang and
Chunhua Qi and
Rongsheng Zhang and
Xuebing Cao and
Liyi Xiao and
Zhigang Mao},
title = {Design of Area-Efficient and Highly Reliable {RHBD} 10T Memory Cell
for Aerospace Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {991--994},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2017.2788439},
doi = {10.1109/TVLSI.2017.2788439},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/0004ZSCHWQZCXM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/0006C18,
author = {Dong Wang and
Pak Kwong Chan},
title = {An Electrical Model for Nanometer {CMOS} Device Stress Effect in Design
and Simulation of Analog Reference Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {958--968},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2794763},
doi = {10.1109/TVLSI.2018.2794763},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/0006C18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AbadS18,
author = {Javad Mohebbi Najm Abad and
Ali Soleimani},
title = {Novel Feature Selection Algorithm for Thermal Prediction Model},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {1831--1844},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2841318},
doi = {10.1109/TVLSI.2018.2841318},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AbadS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AbdelfattahR18,
author = {Moataz Abdelfattah and
Gordon W. Roberts},
title = {Cascade and {LC} Ladder-Based Filter Realizations Using Synchronous
Time-Mode Signal Processing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1788--1801},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2828301},
doi = {10.1109/TVLSI.2018.2828301},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AbdelfattahR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AbtahiSKM18,
author = {Tahmid Abtahi and
Colin Shea and
Amey M. Kulkarni and
Tinoosh Mohsenin},
title = {Accelerating Convolutional Neural Network With {FFT} on Embedded Hardware},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1737--1749},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2825145},
doi = {10.1109/TVLSI.2018.2825145},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AbtahiSKM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AdegbijaG18,
author = {Tosiron Adegbija and
Ann Gordon{-}Ross},
title = {PhLock: {A} Cache Energy Saving Technique Using Phase-Based Cache
Locking},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {110--121},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2757477},
doi = {10.1109/TVLSI.2017.2757477},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AdegbijaG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AgarwalK18,
author = {Sukarn Agarwal and
Hemangee K. Kapoor},
title = {Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries
for Energy-Efficient Hybrid Caches},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {1881--1894},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2836156},
doi = {10.1109/TVLSI.2018.2836156},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AgarwalK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AgarwalKPH18,
author = {Pawan Agarwal and
Jong{-}Hoon Kim and
Partha Pratim Pande and
Deukhyoun Heo},
title = {Zero-Power Feed-Forward Spur Cancelation for Supply-Regulated {CMOS}
Ring PLLs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {4},
pages = {653--662},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2788882},
doi = {10.1109/TVLSI.2017.2788882},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AgarwalKPH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AkbariHM18,
author = {Meysam Akbari and
Omid Hashemipour and
Farshad Moradi},
title = {Input Offset Estimation of {CMOS} Integrated Circuits in Weak Inversion},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1812--1816},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2830749},
doi = {10.1109/TVLSI.2018.2830749},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AkbariHM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AliLLH18,
author = {Karim Ali and
Fei Li and
Sunny Y. H. Lua and
Chun{-}Huat Heng},
title = {Energy- and Area-Efficient Spin-Orbit Torque Nonvolatile Flip-Flop
for Power Gating Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {4},
pages = {630--638},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2787664},
doi = {10.1109/TVLSI.2017.2787664},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AliLLH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AljafarPAT18,
author = {Muayad J. Aljafar and
Marek A. Perkowski and
John M. Acken and
Robin Tan},
title = {A Time-Efficient CMOS-Memristive Programmable Circuit Realizing Logic
Functions in Generalized {AND-XOR} Structures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {23--36},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2750074},
doi = {10.1109/TVLSI.2017.2750074},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AljafarPAT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ArafinQ18,
author = {Md Tanvir Arafin and
Gang Qu},
title = {Memristors for Secret Sharing-Based Lightweight Authentication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2671--2683},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2823714},
doi = {10.1109/TVLSI.2018.2823714},
timestamp = {Tue, 14 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ArafinQ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AzharAK18,
author = {Mahmood J. Azhar and
Fathi Amsaad and
Sel{\c{c}}uk K{\"{o}}se},
title = {Duty-Cycle-Based Controlled Physical Unclonable Function},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1647--1658},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2827238},
doi = {10.1109/TVLSI.2018.2827238},
timestamp = {Wed, 05 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AzharAK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BagheriyeTSM18,
author = {Leila Bagheriye and
Siroos Toofan and
Roghayeh Saeidi and
Farshad Moradi},
title = {Offset-Compensated High-Speed Sense Amplifier for STT-MRAMs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1051--1058},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2808140},
doi = {10.1109/TVLSI.2018.2808140},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BagheriyeTSM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BalRC18,
author = {Aatreyi Bal and
Sanghamitra Roy and
Koushik Chakraborty},
title = {Trident: Comprehensive Choke Error Mitigation in {NTC} Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2195--2204},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2863954},
doi = {10.1109/TVLSI.2018.2863954},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BalRC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BalSRC18,
author = {Aatreyi Bal and
Shamik Saha and
Sanghamitra Roy and
Koushik Chakraborty},
title = {Dynamic Choke Sensing for Timing Error Resilience in {NTC} Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {1--10},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2752963},
doi = {10.1109/TVLSI.2017.2752963},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BalSRC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BalachandranCB18,
author = {Arya Balachandran and
Yong Chen and
Chirn Chye Boon},
title = {A 0.013-mm\({}^{\mbox{2}}\) 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer
Under 21-dB Channel Loss in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {599--603},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2771429},
doi = {10.1109/TVLSI.2017.2771429},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BalachandranCB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaylonYGMMPH18,
author = {Joe Baylon and
Xinmin Yu and
Srinivasan Gopal and
Reza Molavi and
Shahriar Mirabbasi and
Partha Pratim Pande and
Deukhyoun Heo},
title = {A 16-Gb/s Low-Power Inductorless Wideband Gain-Boosted Baseband Amplifier
With Skewed Differential Topology for Wireless Network-on-Chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2406--2418},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2856890},
doi = {10.1109/TVLSI.2018.2856890},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BaylonYGMMPH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BelliziaBMSTT18,
author = {Davide Bellizia and
Simone Bongiovanni and
Pietro Monsurr{\`{o}} and
Giuseppe Scotti and
Alessandro Trifiletti and
Francesco Bruno Trotta},
title = {Secure Double Rate Registers as an {RTL} Countermeasure Against Power
Analysis Attacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1368--1376},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2816914},
doi = {10.1109/TVLSI.2018.2816914},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BelliziaBMSTT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BenacerBS18,
author = {Imad Benacer and
Fran{\c{c}}ois{-}Raymond Boyer and
Yvon Savaria},
title = {A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {1939--1952},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2838044},
doi = {10.1109/TVLSI.2018.2838044},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BenacerBS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BhatSUO18,
author = {Ganapati Bhat and
Gaurav Singla and
Ali K. Unver and
{\"{U}}mit Y. Ogras},
title = {Algorithmic Optimization of Thermal and Power Management for Heterogeneous
Mobile Platforms},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {544--557},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2770163},
doi = {10.1109/TVLSI.2017.2770163},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BhatSUO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BhowmikBDB18,
author = {Biswajit Bhowmik and
Santosh Biswas and
Jatindra Kumar Deka and
Bhargab B. Bhattacharya},
title = {Reliability-Aware Test Methodology for Detecting Short-Channel Faults
in On-Chip Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1026--1039},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2803478},
doi = {10.1109/TVLSI.2018.2803478},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BhowmikBDB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BonnoitZN18,
author = {Thierry Bonnoit and
Nacer{-}Eddine Zergainoh and
Michael Nicolaidis},
title = {Reducing Rollback Cost in {VLSI} Circuits to Improve Fault Tolerance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1438--1451},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2818021},
doi = {10.1109/TVLSI.2018.2818021},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BonnoitZN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BuscarinoCFC18,
author = {Arturo Buscarino and
Claudia Corradino and
Luigi Fortuna and
Leon O. Chua},
title = {Taming Spatiotemporal Chaos in Forced Memristive Arrays},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2947--2954},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2833291},
doi = {10.1109/TVLSI.2018.2833291},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BuscarinoCFC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CaiZXFLH18,
author = {Xin Cai and
Mingda Zhou and
Tian Xia and
Wai H. Fong and
Wing{-}Tsz Lee and
Xinming Huang},
title = {Low-Power {SDR} Design on an {FPGA} for Intersatellite Communications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2419--2430},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2850746},
doi = {10.1109/TVLSI.2018.2850746},
timestamp = {Wed, 01 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/CaiZXFLH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Chakrabarty18,
author = {Krishnendu Chakrabarty},
title = {Editorial},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2579--2580},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2881850},
doi = {10.1109/TVLSI.2018.2881850},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Chakrabarty18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChakrabortyBS18,
author = {Supriya Chakraborty and
Tinish Bhattacharya and
Manan Suri},
title = {Current Optimized Coset Coding for Efficient {RRAM} Programming},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {1000--1004},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2791528},
doi = {10.1109/TVLSI.2018.2791528},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChakrabortyBS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CheSP18,
author = {Wenjie Che and
Fareena Saqib and
Jim Plusquellic},
title = {Novel Offset Techniques for Improving Bitstring Quality of a Hardware-Embedded
Delay {PUF}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {4},
pages = {733--743},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2785270},
doi = {10.1109/TVLSI.2017.2785270},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CheSP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenCAC18,
author = {Po{-}Hung Chen and
Hao{-}Chung Cheng and
Yi{-}An Ai and
Wang{-}Ting Chung},
title = {Automatic Mode-Selected Energy Harvesting Interface With {\textgreater}80{\%}
Power Efficiency Over 200 nW to 10 mW},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2898--2906},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2864922},
doi = {10.1109/TVLSI.2018.2864922},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenCAC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenCCWS18,
author = {Shuo{-}Han Chen and
Yen{-}Ting Chen and
Yuan{-}Hao Chang and
Hsin{-}Wen Wei and
Wei{-}Kuan Shih},
title = {A Progressive Performance Boosting Strategy for 3-D Charge-Trap {NAND}
Flash},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2322--2334},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2856080},
doi = {10.1109/TVLSI.2018.2856080},
timestamp = {Tue, 05 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenCCWS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenEGGYMWG18,
author = {Dongliang Chen and
Jonathon Edstrom and
Yifu Gong and
Peng Gao and
Lei Yang and
Mark E. McCourt and
Jinhui Wang and
Na Gong},
title = {Viewer-Aware Intelligent Efficient Mobile Video Embedded Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {4},
pages = {684--696},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2787043},
doi = {10.1109/TVLSI.2017.2787043},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenEGGYMWG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenHCKY18,
author = {Jiann{-}Jong Chen and
Yuh{-}Shyan Hwang and
Jianhan Chen and
Yi{-}Tsen Ku and
Cheng{-}Chieh Yu},
title = {A New Fast-Response Current-Mode Buck Converter With Improved I\({}^{\mbox{2}}\)-Controlled
Techniques},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {903--911},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2796088},
doi = {10.1109/TVLSI.2018.2796088},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenHCKY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenLLC18,
author = {Xiaowen Chen and
Yuanwu Lei and
Zhonghai Lu and
Shuming Chen},
title = {A Variable-Size {FFT} Hardware Accelerator Based on Matrix Transposition},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {1953--1966},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2846688},
doi = {10.1109/TVLSI.2018.2846688},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenLLC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenPFGW18,
author = {Xiaowei Chen and
Seyed Alireza Pourbakhsh and
Jingyan Fu and
Na Gong and
Jinhui Wang},
title = {A Novel Hybrid Delay Unit Based on Dummy TSVs for 3-D On-Chip Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1277--1289},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2809961},
doi = {10.1109/TVLSI.2018.2809961},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenPFGW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenWXG18,
author = {Zhengyu Chen and
Huanyu Wang and
Geng Xie and
Jie Gu},
title = {A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency
in Voltage-Scalable Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2118--2131},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2847622},
doi = {10.1109/TVLSI.2018.2847622},
timestamp = {Fri, 11 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenWXG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenY18,
author = {Xiaobai Chen and
Zhiyi Yu},
title = {A Flexible and Energy-Efficient Convolutional Neural Network Acceleration
With Dedicated {ISA} and Accelerator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1408--1412},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2810831},
doi = {10.1109/TVLSI.2018.2810831},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChittamuruTP18,
author = {Sai Vineel Reddy Chittamuru and
Ishan G. Thakkar and
Sudeep Pasricha},
title = {{HYDRA:} Heterodyne Crosstalk Mitigation With Double Microring Resonators
and Data Encoding for Photonic NoCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {168--181},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2749967},
doi = {10.1109/TVLSI.2017.2749967},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChittamuruTP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChungYTC18,
author = {Yung{-}Hui Chung and
Chia{-}Wei Yen and
Pei{-}Kang Tsai and
Bo{-}Wei Chen},
title = {A 12-bit 40-MS/s {SAR} {ADC} With a Fast-Binary-Window {DAC} Switching
Scheme},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {1989--1998},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2849008},
doi = {10.1109/TVLSI.2018.2849008},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChungYTC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CiprutF18,
author = {Albert Ciprut and
Eby G. Friedman},
title = {Energy-Efficient Write Scheme for Nonvolatile Resistive Crossbar Arrays
With Selectors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {4},
pages = {711--719},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2785740},
doi = {10.1109/TVLSI.2017.2785740},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CiprutF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ClarkMK18,
author = {Lawrence T. Clark and
Sai Bharadwaj Medapuram and
Divya Kiran Kadiyala},
title = {{SRAM} Circuits for True Random Number Generation Using Intrinsic
Bit Instability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2027--2037},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2840049},
doi = {10.1109/TVLSI.2018.2840049},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ClarkMK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CookSDST18,
author = {Chase Cook and
Zeyu Sun and
Ertugrul Demircan and
Mehul D. Shroff and
Sheldon X.{-}D. Tan},
title = {Fast Electromigration Stress Evolution Analysis for Interconnect Trees
Using Krylov Subspace Method},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {969--980},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2800707},
doi = {10.1109/TVLSI.2018.2800707},
timestamp = {Fri, 19 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CookSDST18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Dai-guoQZLLCS18,
author = {Daiguo Xu and
Lei Qiu and
Zhengping Zhang and
Tao Liu and
Lu Liu and
Kairang Chen and
Shiliu Xu},
title = {A Linearity-Improved 8-bit 320-MS/s {SAR} {ADC} With Metastability
Immunity Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1545--1553},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2822678},
doi = {10.1109/TVLSI.2018.2822678},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Dai-guoQZLLCS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DallooNO18,
author = {Ayad Dalloo and
Ardalan Najafi and
Alberto Garc{\'{\i}}a Ortiz},
title = {Systematic Design of an Approximate Adder: The Optimized Lower Part
Constant-OR Adder},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1595--1599},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2822278},
doi = {10.1109/TVLSI.2018.2822278},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DallooNO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DiguetORSBH18,
author = {Jean{-}Philippe Diguet and
Naoya Onizawa and
Mostafa Rizk and
Martha Johanna Sep{\'{u}}lveda and
Amer Baghdadi and
Takahiro Hanyu},
title = {Networked Power-Gated MRAMs for Memory-Based Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2696--2708},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2856458},
doi = {10.1109/TVLSI.2018.2856458},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DiguetORSBH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DingHCBLBPR18,
author = {Ming Ding and
Pieter Harpe and
Guibin Chen and
Benjamin Busze and
Yao{-}Hong Liu and
Christian Bachmann and
Kathleen Philips and
Arthur H. M. van Roermund},
title = {A Hybrid Design Automation Tool for {SAR} ADCs in IoT},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2853--2862},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2865404},
doi = {10.1109/TVLSI.2018.2865404},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DingHCBLBPR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DongZ18,
author = {Xuan Dong and
Lihong Zhang},
title = {Analog Layout Retargeting With Process-Variation-Aware Hybrid {OPC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {594--598},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2773481},
doi = {10.1109/TVLSI.2017.2773481},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DongZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DuanZH18,
author = {Shengyu Duan and
Mark Zwolinski and
Basel Halak},
title = {Lifetime Reliability-Aware Digital Synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2205--2216},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2861820},
doi = {10.1109/TVLSI.2018.2861820},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DuanZH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/El-HalwagyMH18,
author = {Waleed El{-}Halwagy and
Pedram Mousavi and
Masum Hossain},
title = {A 100-MS/s-5-GS/s, 13-5-bit Nyquist-Rate Reconfigurable Time-Domain
{ADC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {1967--1979},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2850806},
doi = {10.1109/TVLSI.2018.2850806},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/El-HalwagyMH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/El-MohandesSS18,
author = {Awny M. El{-}Mohandes and
Ahmed Shalaby and
Mohammed Sharaf Sayed},
title = {Efficient Low-Power Digital Baseband Transceiver for {IEEE} 802.15.6
Narrowband Physical Layer},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2372--2385},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2862348},
doi = {10.1109/TVLSI.2018.2862348},
timestamp = {Wed, 01 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/El-MohandesSS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ErozanMGBDAT18,
author = {Ahmet Turan Erozan and
Gabriel Cadilha Marques and
Mohammad Saber Golanbari and
Rajendra Bishnoi and
Simone Dehm and
Jasmin Aghassi{-}Hagmann and
Mehdi Baradaran Tahoori},
title = {Inkjet-Printed EGFET-Based Physical Unclonable Function - Design,
Evaluation, and Fabrication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2935--2946},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2866188},
doi = {10.1109/TVLSI.2018.2866188},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ErozanMGBDAT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EshraghianCZNIL18,
author = {Jason Kamran Eshraghian and
Kyoung{-}Rok Cho and
Ciyan Zheng and
Minho Nam and
Herbert Ho{-}Ching Iu and
Wen Lei and
Kamran Eshraghian},
title = {Neuromorphic Vision Hybrid {RRAM-CMOS} Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2816--2829},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2829918},
doi = {10.1109/TVLSI.2018.2829918},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/EshraghianCZNIL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FanWCLW18,
author = {Xitian Fan and
Di Wu and
Wei Cao and
Wayne Luk and
Lingli Wang},
title = {Stream Processing Dual-Track {CGRA} for Object Inference},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1098--1111},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2797600},
doi = {10.1109/TVLSI.2018.2797600},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FanWCLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FardadSY18,
author = {Mohammad Fardad and
Sayed Masoud Sayedi and
Ehsan Yazdian},
title = {Hardware Implementation of Iterative Method With Adaptive Thresholding
for Random Sampling Recovery of Sparse Signals},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {867--877},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2791351},
doi = {10.1109/TVLSI.2018.2791351},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FardadSY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FreudenbergerRS18,
author = {J{\"{u}}rgen Freudenberger and
Mohammed Rajab and
Sergo Shavgulidze},
title = {A Source and Channel Coding Approach for Improving Flash Memory Endurance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {981--990},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2797078},
doi = {10.1109/TVLSI.2018.2797078},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FreudenbergerRS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FuP18,
author = {Zhongyi Fu and
Kong{-}Pang Pun},
title = {An {SAR} {ADC} Switching Scheme With {MSB} Prediction for a Wide Input
Range and Reduced Reference Voltage},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2863--2872},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2866515},
doi = {10.1109/TVLSI.2018.2866515},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FuP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GaoJLRM18,
author = {Zhen Gao and
Qingqing Jing and
Yumeng Li and
Pedro Reviriego and
Juan Antonio Maestro},
title = {An Efficient Fault-Tolerance Design for Integer Parallel Matrix-Vector
Multiplications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {211--215},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2755765},
doi = {10.1109/TVLSI.2017.2755765},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GaoJLRM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GebregiorgisT18,
author = {Anteneh Gebregiorgis and
Mehdi Baradaran Tahoori},
title = {Fine-Grained Energy-Constrained Microprocessor Pipeline Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {457--469},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2767543},
doi = {10.1109/TVLSI.2017.2767543},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GebregiorgisT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GeorgeLLMSMASGN18,
author = {Sumitha George and
Xueqing Li and
Minli Julie Liao and
Kaisheng Ma and
Srivatsa Rangachar Srinivasa and
Karthik Mohan and
Ahmedullah Aziz and
John Sampson and
Sumeet Kumar Gupta and
Vijaykrishnan Narayanan},
title = {Symmetric 2-D-Memory Access to Multidimensional Data},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1040--1050},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2801302},
doi = {10.1109/TVLSI.2018.2801302},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GeorgeLLMSMASGN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GhanaatianBMMMT18,
author = {Reza Ghanaatian and
Alexios Balatsoukas{-}Stimming and
Thomas Christoph M{\"{u}}ller and
Michael Meidlinger and
Gerald Matz and
Adam Teman and
Andreas Burg},
title = {A 588-Gb/s {LDPC} Decoder Based on Finite-Alphabet Message Passing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {329--340},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2766925},
doi = {10.1109/TVLSI.2017.2766925},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GhanaatianBMMMT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GharpindeTDS18,
author = {Rahul Gharpinde and
Phrangboklang Lyngton Thangkhiew and
Kamalika Datta and
Indranil Sengupta},
title = {A Scalable In-Memory Logic Synthesis Approach Using Memristor Crossbar},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {355--366},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2763171},
doi = {10.1109/TVLSI.2017.2763171},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GharpindeTDS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GimenoBF18,
author = {Cecilia Gimeno and
David Bol and
Denis Flandre},
title = {Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1807--1811},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2826440},
doi = {10.1109/TVLSI.2018.2826440},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GimenoBF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GiriCR18,
author = {Davide Giri and
Giovanni Causapruno and
Fabrizio Riente},
title = {Parallel and Serial Computation in Nanomagnet Logic: An Overview},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1427--1437},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2821107},
doi = {10.1109/TVLSI.2018.2821107},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GiriCR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GitermanVLWKF18,
author = {Robert Giterman and
Maoz Vicentowski and
Itamar Levi and
Yoav Weizman and
Osnat Keren and
Alexander Fish},
title = {Leakage Power Attack-Resilient Symmetrical 8T {SRAM} Cell},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2180--2184},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2840132},
doi = {10.1109/TVLSI.2018.2840132},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GitermanVLWKF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GnadOKT18,
author = {Dennis R. E. Gnad and
Fabian Oboril and
Saman Kiamehr and
Mehdi Baradaran Tahoori},
title = {An Experimental Evaluation and Analysis of Transient Voltage Fluctuations
in FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {1817--1830},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2848460},
doi = {10.1109/TVLSI.2018.2848460},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GnadOKT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GopalDAAHP18,
author = {Srinivasan Gopal and
Sourav Das and
Pawan Agarwal and
Sheikh Nijam Ali and
Deukhyoun Heo and
Partha Pratim Pande},
title = {High-Performance and Small-Form Factor Near-Field Inductive Coupling
for 3-D NoC},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2921--2934},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2865704},
doi = {10.1109/TVLSI.2018.2865704},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GopalDAAHP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GovindarajGK18,
author = {Rekha Govindaraj and
Swaroop Ghosh and
Srinivas Katkoori},
title = {CSRO-Based Reconfigurable True Random Number Generator Using {RRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2661--2670},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2823274},
doi = {10.1109/TVLSI.2018.2823274},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GovindarajGK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Gracia-MoranSGG18,
author = {Joaquin Gracia{-}Moran and
Luis J. Saiz{-}Adalid and
Daniel Gil{-}Tomas and
Pedro J. Gil{-}Vicente},
title = {Improving Error Correction Codes for Multiple-Cell Upsets in Space
Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2132--2142},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2837220},
doi = {10.1109/TVLSI.2018.2837220},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Gracia-MoranSGG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GrossiVZRNGPON18,
author = {Alessandro Grossi and
Elisa Vianello and
Cristian Zambelli and
Pablo Royer and
Jean{-}Philippe Noel and
Bastien Giraud and
Luca Perniola and
Piero Olivo and
Etienne Nowak},
title = {Experimental Investigation of 4-kb {RRAM} Arrays Programming Conditions
Suitable for {TCAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2599--2607},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2805470},
doi = {10.1109/TVLSI.2018.2805470},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GrossiVZRNGPON18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuinZS18,
author = {Ujjwal Guin and
Ziqi Zhou and
Adit D. Singh},
title = {Robust Design-for-Security Architecture for Enabling Trust in {IC}
Manufacturing and Test},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {818--830},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2797019},
doi = {10.1109/TVLSI.2018.2797019},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuinZS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GulerJ18,
author = {Abdullah Guler and
Niraj K. Jha},
title = {Hybrid Monolithic 3-D {IC} Floorplanner},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {1868--1880},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2832607},
doi = {10.1109/TVLSI.2018.2832607},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GulerJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuoXRTF18,
author = {Zimu Guo and
Xiaolin Xu and
Md. Tauhidur Rahman and
Mark M. Tehranipoor and
Domenic Forte},
title = {SCARe: An SRAM-Based Countermeasure Against {IC} Recycling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {4},
pages = {744--755},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2777262},
doi = {10.1109/TVLSI.2017.2777262},
timestamp = {Wed, 15 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuoXRTF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HalawaniLMAA18,
author = {Yasmin Halawani and
Muath Abu Lebdeh and
Baker Mohammad and
Mahmoud Al{-}Qutayri and
Said F. Al{-}Sarawi},
title = {Stateful Memristor-Based Search Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2773--2780},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2812800},
doi = {10.1109/TVLSI.2018.2812800},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HalawaniLMAA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HalawaniMAA18,
author = {Yasmin Halawani and
Baker Mohammad and
Mahmoud Al{-}Qutayri and
Said F. Al{-}Sarawi},
title = {Memristor-Based Hardware Accelerator for Image Compression},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2749--2758},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2835572},
doi = {10.1109/TVLSI.2018.2835572},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HalawaniMAA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HamdiouiGFR18,
author = {Said Hamdioui and
Pierre{-}Emmanuel Gaillardon and
Dietmar Fey and
Tajana Simunic Rosing},
title = {Guest Editorial Memristive-Device-Based Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2581--2583},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2878679},
doi = {10.1109/TVLSI.2018.2878679},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HamdiouiGFR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HameedKC18,
author = {Fazal Hameed and
Asif Ali Khan and
Jer{\'{o}}nimo Castrill{\'{o}}n},
title = {Performance and Energy-Efficient Design of {STT-RAM} Last-Level Cache},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1059--1072},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2804938},
doi = {10.1109/TVLSI.2018.2804938},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HameedKC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HasanuzzamanMMH18,
author = {Md. Hasanuzzaman and
Bahareh Ghane Motlagh and
Fay{\c{c}}al Mouna{\"{\i}}m and
Ahmad Hassan and
Rabin Raut and
Mohamad Sawan},
title = {Toward an Energy-Efficient High-Voltage Compliant Visual Intracortical
Multichannel Stimulator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {878--891},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2794445},
doi = {10.1109/TVLSI.2018.2794445},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HasanuzzamanMMH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HassanSS18,
author = {Ahmad Hassan and
Yvon Savaria and
Mohamad Sawan},
title = {Electronics and Packaging Intended for Emerging Harsh Environment
Applications: {A} Review},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2085--2098},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2834499},
doi = {10.1109/TVLSI.2018.2834499},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HassanSS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeWDBD18,
author = {Zhangqing He and
Meilin Wan and
Jie Deng and
Chuang Bai and
Kui Dai},
title = {A Reliable Strong {PUF} Based on Switched-Capacitor Circuit},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1073--1083},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2806041},
doi = {10.1109/TVLSI.2018.2806041},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HeWDBD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HoCNGC18,
author = {Weng{-}Geng Ho and
Kwen{-}Siong Chong and
Kyaw Zwa Lwin Ne and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {Asynchronous-Logic {QDI} Quad-Rail Sense-Amplifier Half-Buffer Approach
for NoC Router Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {196--200},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2750171},
doi = {10.1109/TVLSI.2017.2750171},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HoCNGC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HongHPC18,
author = {JuHyung Hong and
Sangwoo Han and
Young Min Park and
Eui{-}Young Chung},
title = {{ICS:} Interrupt-Based Channel Sneaking for Maximally Exploiting Die-Level
Parallelism of {NAND} Flash-Based Storage Devices},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1802--1806},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2824818},
doi = {10.1109/TVLSI.2018.2824818},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HongHPC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HsiehW18,
author = {Jui{-}Hung Hsieh and
Hung{-}Ren Wang},
title = {{VLSI} Design of an ML-Based Power-Efficient Motion Estimation Controller
for Intelligent Mobile Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {262--271},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2764043},
doi = {10.1109/TVLSI.2017.2764043},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HsiehW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HsuCLC18,
author = {Kai{-}Hsiang Hsu and
Yung{-}Chih Chen and
You{-}Luen Lee and
Shih{-}Chieh Chang},
title = {Contactless Testing for Prebond Interposers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1005--1014},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2805850},
doi = {10.1109/TVLSI.2018.2805850},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HsuCLC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Huang18,
author = {Pengda Huang},
title = {Study on a Low-Complexity {ECG} Compression Scheme With Two-Tier Sensors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2155--2159},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2852751},
doi = {10.1109/TVLSI.2018.2852751},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Huang18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangLYDC18,
author = {Ing{-}Jer Huang and
Chun{-}Hung Lai and
Yun{-}Chung Yang and
Hsu{-}Kang Dow and
Hung{-}Lun Chen},
title = {A Reconfigurable Cache for Efficient Use of Tag {RAM} as Scratch-Pad
Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {4},
pages = {663--670},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2785222},
doi = {10.1109/TVLSI.2017.2785222},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangLYDC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HwangCSK18,
author = {Yuh{-}Shyan Hwang and
Jiann{-}Jong Chen and
Rong{-}Lian Shih and
Yi{-}Tsen Ku},
title = {A 2- {\textdollar}{\textbackslash}mu {\textbackslash}text\{s\}{\textdollar}
Fast-Response Step-Up Converter With Efficiency-Enhancement Techniques
Suitable for Cluster-Based Wireless Sensor Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {216--220},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2761403},
doi = {10.1109/TVLSI.2017.2761403},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HwangCSK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/IslamFLG18,
author = {Riadul Islam and
Hany Ahmed Fahmy and
Ping{-}Yao Lin and
Matthew R. Guthaus},
title = {{DCMCS:} Highly Robust Low-Power Differential Current-Mode Clocking
and Synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2108--2117},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2837681},
doi = {10.1109/TVLSI.2018.2837681},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/IslamFLG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JainRRR18,
author = {Shubham Jain and
Ashish Ranjan and
Kaushik Roy and
Anand Raghunathan},
title = {Computing in Memory With Spin-Transfer Torque Magnetic {RAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {470--483},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2776954},
doi = {10.1109/TVLSI.2017.2776954},
timestamp = {Thu, 20 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JainRRR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JeongOSJ18,
author = {Hanwool Jeong and
Tae Woo Oh and
Seung Chul Song and
Seong{-}Ook Jung},
title = {Sense-Amplifier-Based Flip-Flop With Transition Completion Detection
for Low-Voltage Operation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {4},
pages = {609--620},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2777788},
doi = {10.1109/TVLSI.2017.2777788},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JeongOSJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JiKPS18,
author = {Youngwoo Ji and
Byungsub Kim and
Hong{-}June Park and
Jae{-}Yoon Sim},
title = {A Study on Bandgap Reference Circuit With Leakage-Based {PTAT} Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2310--2321},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2852802},
doi = {10.1109/TVLSI.2018.2852802},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JiKPS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JinKJKC18,
author = {Ja{-}Hoon Jin and
Seok Kim and
Xuefan Jin and
Sang{-}Hoon Kim and
Jung{-}Hoon Chun},
title = {A 12.5-Gb/s Near-Ground Transceiver Employing a MaxEye Algorithm-Based
Adaptation Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {522--530},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2773642},
doi = {10.1109/TVLSI.2017.2773642},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JinKJKC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JindalPS18,
author = {Neetu Jindal and
Preeti Ranjan Panda and
Smruti R. Sarangi},
title = {Reusing Trace Buffers as Victim Caches},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1699--1712},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2827928},
doi = {10.1109/TVLSI.2018.2827928},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JindalPS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JoKC18,
author = {Youngwoo Jo and
Hyojun Kim and
SeongHwan Cho},
title = {A 3.2-GHz Supply Noise-Insensitive {PLL} Using a Gate-Voltage-Boosted
Source-Follower Regulator and Residual Noise Cancellation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2170--2174},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2845859},
doi = {10.1109/TVLSI.2018.2845859},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JoKC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JuandaSC18,
author = {F. N. U. Juanda and
Wei Shu and
Joseph S. Chang},
title = {A Calibration-Free/DEM-Free 8-bit 2.4-GS/s Single-Core Digital-to-Analog
Converter With a Distributed Biasing Scheme},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2299--2309},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2850919},
doi = {10.1109/TVLSI.2018.2850919},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JuandaSC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JungRPJ18,
author = {Dong{-}Hoon Jung and
Kyungho Ryu and
Jung{-}Hyun Park and
Seong{-}Ook Jung},
title = {All-Digital Process-Variation-Calibrated Timing Generator for {ATE}
With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1015--1025},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2801030},
doi = {10.1109/TVLSI.2018.2801030},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JungRPJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JuracyMKA18,
author = {Leonardo Rezende Juracy and
Matheus T. Moreira and
Felipe A. Kuentzer and
Alexandre M. Amory},
title = {A DfT Insertion Methodology to Scannable Q-Flop Elements},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1609--1612},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2821134},
doi = {10.1109/TVLSI.2018.2821134},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JuracyMKA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhanIG18,
author = {Mohammad Nasim Imtiaz Khan and
Anirudh Iyengar and
Swaroop Ghosh},
title = {Novel Magnetic Burn-In for Retention and Magnetic Tolerance Testing
of {STTRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1508--1517},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2820508},
doi = {10.1109/TVLSI.2018.2820508},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KhanIG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhoramiS18,
author = {Ata Khorami and
Mohammad Sharifkhani},
title = {A Low-Power High-Speed Comparator for Precise Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2038--2049},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2833037},
doi = {10.1109/TVLSI.2018.2833037},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KhoramiS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimBDLSLWCPC18,
author = {Jaemin Kim and
Donkyu Baek and
Caiwen Ding and
Sheng Lin and
Donghwa Shin and
Xue Lin and
Yanzhi Wang and
Youngjin Cho and
Sang Hyun Park and
Naehyuck Chang},
title = {Dynamic Reconfiguration of Thermoelectric Generators for Vehicle Radiators
Energy Harvesting Under Location-Dependent Temperature Variations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1241--1253},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2812705},
doi = {10.1109/TVLSI.2018.2812705},
timestamp = {Tue, 21 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KimBDLSLWCPC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimCKKDC18,
author = {Jongho Kim and
Kiyoung Choi and
Yonghwan Kim and
Wook Kim and
Kyung Tae Do and
Jung{-}Hwan Choi},
title = {Delay Monitoring System With Multiple Generic Monitors for Wide Voltage
Range Operation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {37--49},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2757511},
doi = {10.1109/TVLSI.2017.2757511},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimCKKDC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimKSPK18,
author = {Kwangmin Kim and
Seokjoon Kang and
Jae{-}Yoon Sim and
Hong{-}June Park and
Byungsub Kim},
title = {A Search Algorithm for the Worst Operation Scenario of a Cross-Point
Phase-Change Memory Utilizing Particle Swarm Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2591--2598},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2855959},
doi = {10.1109/TVLSI.2018.2855959},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimKSPK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimLK18,
author = {Donghyun Kim and
Hayoung Lee and
Sungho Kang},
title = {An Area-Efficient {BIRA} With 1-D Spare Segments},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {206--210},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2752298},
doi = {10.1109/TVLSI.2017.2752298},
timestamp = {Tue, 27 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimLK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimNYK18,
author = {Susie Kim and
Seung{-}In Na and
Youngtae Yang and
Suhwan Kim},
title = {A 2-MHz {BW} 82-dB {DR} Continuous-Time Delta-Sigma Modulator With
a Capacitor-Based Voltage {DAC} for {ELD} Compensation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {1999--2006},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2841058},
doi = {10.1109/TVLSI.2018.2841058},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimNYK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimSCKC18,
author = {Jaemin Kim and
Donghwa Shin and
Nam Ik Cho and
Byunghee Kang and
Naehyuck Chang},
title = {Aging Management Using a Reconfigurable Switch Network for Arrays
of Nonideal Power Cells},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {855--866},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2800700},
doi = {10.1109/TVLSI.2018.2800700},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimSCKC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KlineXMJ18,
author = {Donald Kline Jr. and
Haifeng Xu and
Rami G. Melhem and
Alex K. Jones},
title = {Racetrack Queues for Extremely Low-Energy FIFOs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1531--1544},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2819945},
doi = {10.1109/TVLSI.2018.2819945},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KlineXMJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KongZG18,
author = {Shuyu Kong and
Hai Zhou and
Jie Gu},
title = {Design and Synthesis of Self-Healing Memristive Circuits for Timing
Resilient Processor Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2648--2660},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2834827},
doi = {10.1109/TVLSI.2018.2834827},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KongZG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KulkarniPAJMHM18,
author = {Adwaya Kulkarni and
Adam Page and
Nasrin Attaran and
Ali Jafari and
Maria Malik and
Houman Homayoun and
Tinoosh Mohsenin},
title = {An Energy-Efficient Programmable Manycore Accelerator for Personalized
Biomedical Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {96--109},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2754272},
doi = {10.1109/TVLSI.2017.2754272},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KulkarniPAJMHM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KulkarniPK18,
author = {Anant Kulkarni and
Sanjay Prajapati and
Brajesh Kumar Kaushik},
title = {Transmission Coefficient Matrix Modeling of Spin-Torque-Based {\textdollar}n{\textdollar}
-Qubit Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1461--1470},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2814041},
doi = {10.1109/TVLSI.2018.2814041},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KulkarniPK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Kung0M18,
author = {Jaeha Kung and
Duckhwan Kim and
Saibal Mukhopadhyay},
title = {Adaptive Precision Cellular Nonlinear Network},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {841--854},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2794498},
doi = {10.1109/TVLSI.2018.2794498},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Kung0M18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeAN18,
author = {Wai{-}Kong Lee and
Ramachandra Achar and
Michel S. Nakhla},
title = {Dynamic {GPU} Parallel Sparse {LU} Factorization for Fast Circuit
Simulation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2518--2529},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2858014},
doi = {10.1109/TVLSI.2018.2858014},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeAN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeH18,
author = {Yu{-}Hsuan Lee and
Meng{-}Ren Huang},
title = {Algorithm and Architecture Design of a Hardware-Efficient Frame Rate
Upconversion Engine},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2553--2566},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2849438},
doi = {10.1109/TVLSI.2018.2849438},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeKKPYLHYL18,
author = {Dong{-}Soo Lee and
Sung{-}Jin Kim and
Donggyu Kim and
YoungGun Pu and
Sang{-}Sun Yoo and
Minjae Lee and
Keum{-}Cheol Hwang and
Youngoo Yang and
Kang{-}Yoon Lee},
title = {A Design of Fast-Settling, Low-Power 4.19-MHz Real-Time Clock Generator
With Temperature Compensation and 15-dB Noise Reduction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1151--1158},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2806935},
doi = {10.1109/TVLSI.2018.2806935},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeKKPYLHYL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeLELCCAW18,
author = {Albert Lee and
Hochul Lee and
Farbod Ebrahimi and
Bonnie Lam and
Wei{-}Hao Chen and
Meng{-}Fan Chang and
Pedram Khalili Amiri and
Kang{-}Lung Wang},
title = {A Dual-Data Line Read Scheme for High-Speed Low-Energy Resistive Nonvolatile
Memories},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {272--279},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2766150},
doi = {10.1109/TVLSI.2017.2766150},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeLELCCAW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeiCLLWZMS18,
author = {Yu Lei and
Houpeng Chen and
Xiaoyun Li and
Xi Li and
Qian Wang and
Qi Zhang and
Jie Miao and
Zhitang Song},
title = {A Changing-Reference Parasitic-Matching Sensing Circuit for 3-D Vertical
{RRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1268--1276},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2816246},
doi = {10.1109/TVLSI.2018.2816246},
timestamp = {Thu, 15 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeiCLLWZMS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeonZSP18,
author = {Vasileios Leon and
Georgios Zervakis and
Dimitrios Soudris and
Kiamal Z. Pekmestzi},
title = {Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact
Multipliers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {421--430},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2767858},
doi = {10.1109/TVLSI.2017.2767858},
timestamp = {Wed, 06 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeonZSP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeviFK18,
author = {Itamar Levi and
Alexander Fish and
Osnat Keren},
title = {Low-Cost Pseudoasynchronous Circuit Design Style With Reduced Exploitable
Side Information},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {82--95},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2757064},
doi = {10.1109/TVLSI.2017.2757064},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeviFK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiDBDP18,
author = {Xian Li and
Karthi Duraisamy and
Paul Bogdan and
Janardhan Rao Doppa and
Partha Pratim Pande},
title = {Scalable Network-on-Chip Architectures for Brain-Machine Interface
Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {1895--1907},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2843282},
doi = {10.1109/TVLSI.2018.2843282},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiDBDP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiLJHYZCC18,
author = {Yan Li and
Yufeng Li and
Jie Han and
Jianhao Hu and
Fan Yang and
Xuan Zeng and
Bruce F. Cockburn and
Jie Chen},
title = {Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular
Redundancy},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1585--1589},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2819896},
doi = {10.1109/TVLSI.2018.2819896},
timestamp = {Wed, 20 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiLJHYZCC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiLLYFYFXHY18,
author = {Jinyang Li and
Yongpan Liu and
Hehe Li and
Zhe Yuan and
Chenchen Fu and
Jinshan Yue and
Xiaoyu Feng and
Chun Jason Xue and
Jingtong Hu and
Huazhong Yang},
title = {{PATH:} Performance-Aware Task Scheduling for Energy-Harvesting Nonvolatile
Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1671--1684},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2825605},
doi = {10.1109/TVLSI.2018.2825605},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiLLYFYFXHY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiRXAL18,
author = {Jiaqiang Li and
Pedro Reviriego and
Liyi Xiao and
Costas Argyrides and
Jie Li},
title = {Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent
Error Correction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {221--229},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2766361},
doi = {10.1109/TVLSI.2017.2766361},
timestamp = {Fri, 13 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiRXAL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiW18,
author = {Chun{-}Hsing Li and
Wei{-}Min Wu},
title = {A Balunless Frequency Multiplier With Differential Output by Current
Flow Manipulation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1391--1402},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2806348},
doi = {10.1109/TVLSI.2018.2806348},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiYOCPZ18,
author = {Xingquan Li and
Bei Yu and
Jiaojiao Ou and
Jianli Chen and
David Z. Pan and
Wenxing Zhu},
title = {Graph-Based Redundant Via Insertion and Guiding Template Assignment
for {DSA-MP}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2504--2517},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2850044},
doi = {10.1109/TVLSI.2018.2850044},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiYOCPZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinCC18,
author = {Cheng{-}Hung Lin and
Sze{-}Chen Cho and
Shih{-}Chieh Chang},
title = {An Adaptive Mechanism for Designing Efficient Snoop Filters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1233--1240},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2810241},
doi = {10.1109/TVLSI.2018.2810241},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinCC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinFCRK18,
author = {Zhi{-}Wen Lin and
Shao{-}Yun Fang and
Yao{-}Wen Chang and
Wei{-}Cheng Rao and
Chieh{-}Hsiung Kuan},
title = {Provably Good Max-Min-\emph{m}-Neighbor-TSP-Based Subfield Scheduling
for Electron-Beam Photomask Fabrication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {378--391},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2761850},
doi = {10.1109/TVLSI.2017.2761850},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinFCRK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinLX18,
author = {Ing{-}Chao Lin and
Yun Kae Law and
Yuan Xie},
title = {Mitigating BTI-Induced Degradation in {STT-MRAM} Sensing Schemes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {50--62},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2764520},
doi = {10.1109/TVLSI.2017.2764520},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinLX18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuEZS18,
author = {Qiyuan Liu and
Alexander Edward and
Dadian Zhou and
Jos{\'{e}} Silva{-}Mart{\'{\i}}nez},
title = {A Continuous-Time {MASH} 1-1-1 Delta-Sigma Modulator With {FIR} {DAC}
and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {4},
pages = {756--767},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2780272},
doi = {10.1109/TVLSI.2017.2780272},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuEZS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuH18,
author = {Siting Liu and
Jie Han},
title = {Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1326--1339},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2812214},
doi = {10.1109/TVLSI.2018.2812214},
timestamp = {Mon, 08 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuHFH18,
author = {Zemin Liu and
Yu{-}Pin Hsu and
Bassem Fahs and
Mona Mostafa Hella},
title = {An {RF-DC} Converter {IC} With On-Chip Adaptive Impedance Matching
and 307- {\textdollar}{\textbackslash}mu{\textdollar} {W} Peak Output
Power for Health Monitoring Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1565--1574},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2822120},
doi = {10.1109/TVLSI.2018.2822120},
timestamp = {Mon, 26 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuHFH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuHL18,
author = {Jen{-}Chieh Liu and
Chao{-}Jen Huang and
Pei{-}Ying Lee},
title = {A High-Accuracy Programmable Pulse Generator With a 10-ps Timing Resolution},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {4},
pages = {621--629},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2781421},
doi = {10.1109/TVLSI.2017.2781421},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuHL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuJLMHZZ18,
author = {Lizheng Liu and
Yi Jin and
Yi Liu and
Ning Ma and
Yuxiang Huan and
Zhuo Zou and
Lirong Zheng},
title = {A Design of Autonomous Error-Tolerant Architectures for Massively
Parallel Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2143--2154},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2846298},
doi = {10.1109/TVLSI.2018.2846298},
timestamp = {Wed, 25 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuJLMHZZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuLSLZZ18,
author = {Qiang Liu and
Jia Liu and
Ruoyu Sang and
Jiajun Li and
Tao Zhang and
Qijun Zhang},
title = {Fast Neural Network Training on {FPGA} Using Quasi-Newton Optimization
Method},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1575--1579},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2820016},
doi = {10.1109/TVLSI.2018.2820016},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuLSLZZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuLW18,
author = {Sujuan Liu and
Ning Lyu and
Haojiang Wang},
title = {The Implementation of the Improved {OMP} for {AIC} Reconstruction
Based on Parallel Index Selection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {319--328},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2765677},
doi = {10.1109/TVLSI.2017.2765677},
timestamp = {Wed, 03 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuPGFKM18,
author = {Jun Liu and
Beomsoo Park and
Marino De Jesus Guzman and
Ahmed Fahmy and
Taewook Kim and
Nima Maghari},
title = {A Fully Synthesized 77-dB {SFDR} Reprogrammable {SRMC} Filter Using
Digital Standard Cells},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1126--1138},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2804220},
doi = {10.1109/TVLSI.2018.2804220},
timestamp = {Wed, 22 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuPGFKM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuXBS18,
author = {Yuntao Liu and
Yang Xie and
Chongxi Bao and
Ankur Srivastava},
title = {A Combined Optimization-Theoretic and Side- Channel Approach for Attacking
Strong Physical Unclonable Functions},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {73--81},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2759731},
doi = {10.1109/TVLSI.2017.2759731},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuXBS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuZW18,
author = {Yang Liu and
Chenchang Zhan and
Lidan Wang},
title = {An Ultralow Power Subthreshold {CMOS} Voltage Reference Without Requiring
Resistors or BJTs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {201--205},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2754442},
doi = {10.1109/TVLSI.2017.2754442},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuZW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LongNM18,
author = {Yun Long and
Taesik Na and
Saibal Mukhopadhyay},
title = {ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural
Network Acceleration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2781--2794},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2819190},
doi = {10.1109/TVLSI.2018.2819190},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LongNM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LowZS18,
author = {Qiong Wei Low and
Mi Zhou and
Liter Siek},
title = {A Single-Stage Direct-Conversion {AC-DC} Converter for Inductively
Powered Application},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {892--902},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2792494},
doi = {10.1109/TVLSI.2018.2792494},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LowZS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuoAZCM18,
author = {Aiwen Luo and
Fengwei An and
Xiangyu Zhang and
Lei Chen and
Hans J{\"{u}}rgen Mattausch},
title = {Resource-Efficient Object-Recognition Coprocessor With Parallel Processing
of Multiple Scan Windows in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {431--444},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2774813},
doi = {10.1109/TVLSI.2017.2774813},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LuoAZCM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuoLNLY18,
author = {Jian Luo and
Jing Li and
Ning Ning and
Yang Liu and
Qi Yu},
title = {A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step {SAR} {ADC} in 40-nm
{CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {1980--1988},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2846746},
doi = {10.1109/TVLSI.2018.2846746},
timestamp = {Mon, 10 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LuoLNLY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LupoBPWM18,
author = {Nicola Lupo and
Edoardo Bonizzoni and
Eduardo P{\'{e}}rez and
Christian Wenger and
Franco Maloberti},
title = {A Voltage-Time Model for Memristive Devices},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1452--1460},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2823586},
doi = {10.1109/TVLSI.2018.2823586},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LupoBPWM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaCVS18,
author = {Yufei Ma and
Yu Cao and
Sarma B. K. Vrudhula and
Jae{-}sun Seo},
title = {Optimizing the Convolution Operation to Accelerate Deep Neural Networks
on {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1354--1367},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2815603},
doi = {10.1109/TVLSI.2018.2815603},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MaCVS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaLR18,
author = {Shunli Ma and
Ning Li and
Junyan Ren},
title = {A 5-to-8-GHz Wideband Miniaturized Dielectric Spectroscopy Chip With
{\textdollar}I/Q{\textdollar} Mismatch Calibration in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1554--1564},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2819702},
doi = {10.1109/TVLSI.2018.2819702},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MaLR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MadhavanSS18,
author = {Advait Madhavan and
Tim Sherwood and
Dmitri B. Strukov},
title = {High-Throughput Pattern Matching With {CMOL} {FPGA} Circuits: Case
for Logic-in-Memory Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2759--2772},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2809644},
doi = {10.1109/TVLSI.2018.2809644},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MadhavanSS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MalikJKSHL18,
author = {Maria Malik and
Rajiv V. Joshi and
Rouwaida Kanj and
Shupeng Sun and
Houman Homayoun and
Tong Li},
title = {Sparse Regression Driven Mixture Importance Sampling for Memory Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {63--72},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2753139},
doi = {10.1109/TVLSI.2017.2753139},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MalikJKSHL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaoLHL18,
author = {Wei Mao and
Yongfu Li and
Chun{-}Huat Heng and
Yong Lian},
title = {High Dynamic Performance Current-Steering {DAC} Design With Nested-Segment
Structure},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {995--999},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2791462},
doi = {10.1109/TVLSI.2018.2791462},
timestamp = {Thu, 29 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MaoLHL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaoYC18,
author = {Manqing Mao and
Shimeng Yu and
Chaitali Chakrabarti},
title = {Design and Analysis of Energy-Efficient and Reliable 3-D ReRAM Cross-Point
Array System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1290--1300},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2814544},
doi = {10.1109/TVLSI.2018.2814544},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MaoYC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MarellaS18,
author = {Sravan K. Marella and
Sachin S. Sapatnekar},
title = {Circuit Performance Shifts Due to Layout-Dependent Stress in Planar
and 3D-ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2907--2920},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2866290},
doi = {10.1109/TVLSI.2018.2866290},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MarellaS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Marino18,
author = {Mario Donato Marino},
title = {Architectural Impacts of RFiop: {RF} to Address {I/O} Pad and Memory
Controller Scalability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1494--1507},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2821004},
doi = {10.1109/TVLSI.2018.2821004},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Marino18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MarinoL18,
author = {Mario Donato Marino and
Kuan{-}Ching Li},
title = {{RAMON:} Region-Aware Memory Controller},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {4},
pages = {697--710},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2789520},
doi = {10.1109/TVLSI.2018.2789520},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MarinoL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MartevHS18,
author = {Dimo Martev and
Sven Hampel and
Ulf Schlichtmann},
title = {Automated Phase-Noise-Aware Design of {RF} Clock Distribution Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2395--2405},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2864316},
doi = {10.1109/TVLSI.2018.2864316},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MartevHS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MasudaOH18,
author = {Yutaka Masuda and
Takao Onoye and
Masanori Hashimoto},
title = {Activation-Aware Slack Assignment for Time-to-Failure Extension and
Power Saving},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2217--2229},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2862154},
doi = {10.1109/TVLSI.2018.2862154},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MasudaOH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MeeusS18,
author = {Wim Meeus and
Dirk Stroobandt},
title = {Data Reuse Buffer Synthesis Using the Polyhedral Model},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1340--1353},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2817159},
doi = {10.1109/TVLSI.2018.2817159},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MeeusS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MilicevicG18,
author = {Mario Milicevic and
P. Glenn Gulak},
title = {A Multi-Gb/s Frame-Interleaved {LDPC} Decoder With Path-Unrolled Message
Passing in 28-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {1908--1921},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2838591},
doi = {10.1109/TVLSI.2018.2838591},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MilicevicG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MiloPCCRAI18,
author = {Valerio Milo and
Giacomo Pedretti and
Roberto Carboni and
Alessandro Calderoni and
Nirmal Ramaswamy and
Stefano Ambrogio and
Daniele Ielmini},
title = {A 4-Transistors/1-Resistor Hybrid Synapse Based on Resistive Switching
Memory {(RRAM)} Capable of Spike-Rate-Dependent Plasticity {(SRDP)}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2806--2815},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2818978},
doi = {10.1109/TVLSI.2018.2818978},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MiloPCCRAI18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MinceySSR18,
author = {John S. Mincey and
Eric C. Su and
Jos{\'{e}} Silva{-}Mart{\'{\i}}nez and
Christopher T. Rodenbeck},
title = {A 128-Tap Highly Tunable {CMOS} {IF} Finite Impulse Response Filter
for Pulsed Radar Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1192--1203},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2803525},
doi = {10.1109/TVLSI.2018.2803525},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MinceySSR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MirajkarCAT18,
author = {Peeyoosh Mirajkar and
Jagdish Chand Goyal and
Sankaran Aniruddhan and
Srinivas Theertham},
title = {Low Phase Noise Ku-Band {VCO} With Optimal Switched-Capacitor Bank
Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {589--593},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2769709},
doi = {10.1109/TVLSI.2017.2769709},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MirajkarCAT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MirzaieASB18,
author = {Nahid Mirzaie and
Ahmed Alzahmi and
Hossein Shamsi and
Gyung{-}Su Byun},
title = {Three-Dimensional Pipeline {ADC} Utilizing {TSV/} Design Optimization
and Memristor Ratioed Logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2619--2627},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2810782},
doi = {10.1109/TVLSI.2018.2810782},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MirzaieASB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MitraN18,
author = {Jubin Mitra and
Tapan Kumar Nayak},
title = {An FPGA-Based Phase Measurement System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {133--142},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2758807},
doi = {10.1109/TVLSI.2017.2758807},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MitraN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MrazekVSJH18,
author = {Vojtech Mrazek and
Zdenek Vas{\'{\i}}cek and
Luk{\'{a}}s Sekanina and
Honglan Jiang and
Jie Han},
title = {Scalable Construction of Approximate Multipliers With Formally Guaranteed
Worst Case Error},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2572--2576},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2856362},
doi = {10.1109/TVLSI.2018.2856362},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MrazekVSJH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MulaGD18,
author = {Subrahmanyam Mula and
Vinay Chakravarthi Gogineni and
Anindya Sundar Dhar},
title = {Algorithm and {VLSI} Architecture Design of Proportionate-Type {LMS}
Adaptive Filters for Sparse System Identification},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1750--1762},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2828165},
doi = {10.1109/TVLSI.2018.2828165},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MulaGD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NajafiLRB18,
author = {M. Hassan Najafi and
David J. Lilja and
Marc D. Riedel and
Kia Bazargan},
title = {Low-Cost Sorting Network Circuits Using Unary Processing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1471--1480},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2822300},
doi = {10.1109/TVLSI.2018.2822300},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NajafiLRB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NambaL18,
author = {Kazuteru Namba and
Fabrizio Lombardi},
title = {On Coding for Endurance Enhancement and Error Control of Phase Change
Memories With Write Latency Reduction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {230--238},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2766362},
doi = {10.1109/TVLSI.2017.2766362},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NambaL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NaminRMA18,
author = {Parham Hosseinzadeh Namin and
Crystal Andrea Roma and
Roberto Muscedere and
Majid Ahmadi},
title = {Efficient {VLSI} Implementation of a Sequential Finite Field Multiplier
Using Reordered Normal Basis in Domino Logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2542--2552},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2851958},
doi = {10.1109/TVLSI.2018.2851958},
timestamp = {Fri, 21 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NaminRMA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NaseriT18,
author = {Hamed Naseri and
Somayeh Timarchi},
title = {Low-Power and Fast Full Adder by Exploring New {XOR} and {XNOR} Gates},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1481--1493},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2820999},
doi = {10.1109/TVLSI.2018.2820999},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NaseriT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NeshatpourBKH18,
author = {Katayoun Neshatpour and
Wayne P. Burleson and
Amin Khajeh and
Houman Homayoun},
title = {Enhancing Power, Performance, and Energy Efficiency in Chip Multiprocessors
Exploiting Inverse Thermal Dependence},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {4},
pages = {778--791},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2780800},
doi = {10.1109/TVLSI.2017.2780800},
timestamp = {Mon, 06 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NeshatpourBKH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Nguyen-LySLDGB18,
author = {Thien Truong Nguyen{-}Ly and
Valentin Savin and
Khoa Le and
David Declercq and
Fakhreddine Ghaffari and
Oana Boncalo},
title = {Analysis and Design of Cost-Effective, High-Throughput {LDPC} Decoders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {508--521},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2776561},
doi = {10.1109/TVLSI.2017.2776561},
timestamp = {Tue, 26 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Nguyen-LySLDGB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NohAZS18,
author = {Kyoohyun Noh and
Judy M. Amanor{-}Boadu and
Minglei Zhang and
Edgar S{\'{a}}nchez{-}Sinencio},
title = {A 13.56-MHz {CMOS} Active Rectifier With a Voltage Mode Switched-Offset
Comparator for Implantable Medical Devices},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2050--2060},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2845369},
doi = {10.1109/TVLSI.2018.2845369},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NohAZS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NourazarRAM18,
author = {Mohsen Nourazar and
Vahid Rashtchi and
Ali Azarpeyvand and
Farshad Merrikh{-}Bayat},
title = {Code Acceleration Using Memristor-Based Approximate Matrix Multiplier:
Application to Convolutional Neural Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2684--2695},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2837908},
doi = {10.1109/TVLSI.2018.2837908},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NourazarRAM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OHareSTM18,
author = {Daniel O'Hare and
Anthony G. Scanlan and
Eric Thompson and
Brendan Mullane},
title = {Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {404--415},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2763129},
doi = {10.1109/TVLSI.2017.2763129},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OHareSTM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OchiYFHKHIDTSTW18,
author = {Hiroyuki Ochi and
Kosei Yamaguchi and
Tetsuaki Fujimoto and
Junshi Hotate and
Takashi Kishimoto and
Toshiki Higashi and
Takashi Imagawa and
Ryutaro Doi and
Munehiro Tada and
Tadahiko Sugibayashi and
Wataru Takahashi and
Kazutoshi Wakabayashi and
Hidetoshi Onodera and
Yukio Mitsuyama and
Jaehoon Yu and
Masanori Hashimoto},
title = {Via-Switch {FPGA:} Highly Dense Mixed-Grained Reconfigurable Architecture
With Overlay Via-Switch Crossbars},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2723--2736},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2812914},
doi = {10.1109/TVLSI.2018.2812914},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OchiYFHKHIDTSTW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OhhataHSIUSM18,
author = {Kenichi Ohhata and
Daiki Hayakawa and
Kenji Sewaki and
Kento Imayanagida and
Kouki Ueno and
Yuuki Sonoda and
Kenichiro Muroya},
title = {A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging {ADC} Combining Flash
{ADC} and {TDC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1777--1787},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2827943},
doi = {10.1109/TVLSI.2018.2827943},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OhhataHSIUSM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OkuharaAKA18,
author = {Hayate Okuhara and
Akram Ben Ahmed and
Johannes Maximilian K{\"{u}}hn and
Hideharu Amano},
title = {Asymmetric Body Bias Control With Low-Power {FD-SOI} Technologies:
Modeling and Power Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1254--1267},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2812893},
doi = {10.1109/TVLSI.2018.2812893},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OkuharaAKA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OnishiSNYNNKOOS18,
author = {Takayuki Onishi and
Takashi Sano and
Yukikuni Nishida and
Kazuya Yokohari and
Ken Nakamura and
Koyo Nitta and
Kimiko Kawashima and
Jun Okamoto and
Naoki Ono and
Atsushi Sagata and
Hiroe Iwasaki and
Mitsuo Ikeda and
Atsushi Shimizu},
title = {A Single-Chip 4K 60-fps 4: 2: 2 {HEVC} Video Encoder {LSI} Employing
Efficient Motion Estimation and Mode Decision Framework With Scalability
to 8K},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {1930--1938},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2842179},
doi = {10.1109/TVLSI.2018.2842179},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OnishiSNYNNKOOS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PagliariniIMP18,
author = {Samuel N. Pagliarini and
Mehmet Meric Isgenc and
Mayler G. A. Martins and
Lawrence T. Pileggi},
title = {Application and Product-Volume-Specific Customization of {BEOL} Metal
Pitch},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1627--1636},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2828387},
doi = {10.1109/TVLSI.2018.2828387},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PagliariniIMP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkY18,
author = {Jaeyoung Park and
Young Uk Yim},
title = {Two-Phase Read Strategy for Low Energy Variation-Tolerant {STT-RAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2584--2590},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2851943},
doi = {10.1109/TVLSI.2018.2851943},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkYPKK18,
author = {Yujin Park and
Junghee Yun and
Dongchul Park and
Sangwoo Kim and
Suhwan Kim},
title = {An Uncooled Microbolometer Infrared Imager With a Shutter-Based Successive-Approximation
Calibration Loop},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {122--132},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2757514},
doi = {10.1109/TVLSI.2017.2757514},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkYPKK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PashaeifarKAP18,
author = {Masoud Pashaeifar and
Mehdi Kamal and
Ali Afzali{-}Kusha and
Massoud Pedram},
title = {Approximate Reverse Carry Propagate Adder for Energy-Efficient {DSP}
Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2530--2541},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2859939},
doi = {10.1109/TVLSI.2018.2859939},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PashaeifarKAP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PassosRCF18,
author = {F{\'{a}}bio Passos and
Elisenda Roca and
Rafael Castro{-}L{\'{o}}pez and
Francisco V. Fern{\'{a}}ndez},
title = {A Comparison of Automated {RF} Circuit Design Methodologies: Online
Versus Offline Passive Component Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2386--2394},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2859827},
doi = {10.1109/TVLSI.2018.2859827},
timestamp = {Thu, 15 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PassosRCF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PathakS18,
author = {Divya Pathak and
Ioannis Savidis},
title = {On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction
Varactors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2230--2240},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2856087},
doi = {10.1109/TVLSI.2018.2856087},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PathakS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PengXLZWCL18,
author = {Chunyu Peng and
Songsong Xiao and
Wenjuan Lu and
Jingbo Zhang and
Xiulong Wu and
Junning Chen and
Zhiting Lin},
title = {Average 7T1R Nonvolatile {SRAM} With {R/W} Margin Enhanced for Low-Power
Application},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {584--588},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2772861},
doi = {10.1109/TVLSI.2017.2772861},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PengXLZWCL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PengZKCT18,
author = {Shaoyi Peng and
Han Zhou and
Taeyoung Kim and
Hai{-}Bao Chen and
Sheldon X.{-}D. Tan},
title = {Physics-Based Compact {TDDB} Models for Low-k {BEOL} Copper Interconnects
With Time-Varying Voltage Stressing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {239--248},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2764880},
doi = {10.1109/TVLSI.2017.2764880},
timestamp = {Wed, 28 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PengZKCT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PerachW18,
author = {Ben Perach and
Shlomo Weiss},
title = {SiMT-DSP: {A} Massively Multithreaded {DSP} Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1413--1426},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2817564},
doi = {10.1109/TVLSI.2018.2817564},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PerachW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PhamL18,
author = {Huyen Thi Pham and
Hanho Lee},
title = {Basic-Set Trellis Min-Max Decoder Architecture for Nonbinary {LDPC}
Codes With High-Order Galois Fields},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {496--507},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2775646},
doi = {10.1109/TVLSI.2017.2775646},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PhamL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PhamVM18,
author = {Thinh Hung Pham and
A. Prasad Vinod and
A. S. Madhukumar},
title = {A Hardware-Efficient Synchronization in {L-DACS1} for Aeronautical
Communications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {924--932},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2789467},
doi = {10.1109/TVLSI.2018.2789467},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PhamVM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz18,
author = {Irith Pomeranz},
title = {Selecting Functional Test Sequences for Defect Diagnosis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2160--2164},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2849972},
doi = {10.1109/TVLSI.2018.2849972},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz18a,
author = {Irith Pomeranz},
title = {Observation Points on State Variables for the Compaction of Multicycle
Tests},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2567--2571},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2854704},
doi = {10.1109/TVLSI.2018.2854704},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PossignoloEASBR18,
author = {Rafael Trapani Possignolo and
Elnaz Ebrahimi and
Ehsan K. Ardestani and
Alamelu Sankaranarayanan and
Jos{\'{e}} Luis Briz and
Jose Renau},
title = {{GPU} {NTC} Process Variation Compensation With Voltage Stacking},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1713--1726},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2831665},
doi = {10.1109/TVLSI.2018.2831665},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PossignoloEASBR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PourashrafRLC18,
author = {Shirin Pourashraf and
Jaime Ram{\'{\i}}rez{-}Angulo and
Antonio J. L{\'{o}}pez{-}Mart{\'{\i}}n and
Ram{\'{o}}n Gonz{\'{a}}lez Carvajal},
title = {A Highly Efficient Composite Class-AB-AB Miller Op-Amp With High Gain
and Stable From 15 pF Up To Very Large Capacitive Loads},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2061--2072},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2830365},
doi = {10.1109/TVLSI.2018.2830365},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PourashrafRLC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PrakashCLS18,
author = {Alok Prakash and
Christopher T. Clarke and
Siew{-}Kei Lam and
Thambipillai Srikanthan},
title = {Rapid Memory-Aware Selection of Hardware Accelerators in Programmable
SoC Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {445--456},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2769125},
doi = {10.1109/TVLSI.2017.2769125},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PrakashCLS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/QiRHHMSNAL18,
author = {Xiaoyuan Qi and
Raymond J. Rosner and
John Hopkins and
Jack M. Higman and
Rick Mewhirter and
Aaron Sinnott and
Binod Kumar G. Nair and
Ishtiaq Ahsan and
Mark Lagus},
title = {A Simplified Yield Model for {SRAM} Repair in Advanced Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2494--2503},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2858561},
doi = {10.1109/TVLSI.2018.2858561},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/QiRHHMSNAL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/QianGHAW18,
author = {Fengyu Qian and
Yanping Gong and
Guoxian Huang and
Mehdi Anwar and
Lei Wang},
title = {Exploiting Memristors for Compressive Sampling of Sensory Signals},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2737--2748},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2840446},
doi = {10.1109/TVLSI.2018.2840446},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/QianGHAW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/QiuTZSZU18,
author = {Lei Qiu and
Kai Tang and
Yuanjin Zheng and
Liter Siek and
Yan Zhu and
Seng{-}Pan U},
title = {A 16-mW 1-GS/s With 49.6-dB {SNDR} {TI-SAR} {ADC} for Software-Defined
Radio in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {572--583},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2771811},
doi = {10.1109/TVLSI.2017.2771811},
timestamp = {Tue, 11 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/QiuTZSZU18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/QiuYWZ18,
author = {Lei Qiu and
Chuanshi Yang and
Keping Wang and
Yuanjin Zheng},
title = {A High-Speed 2-bit/Cycle {SAR} {ADC} With Time-Domain Quantization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2175--2179},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2837030},
doi = {10.1109/TVLSI.2018.2837030},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/QiuYWZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RahaJSJRR18,
author = {Arnab Raha and
Akhilesh Jaiswal and
Syed Shakib Sarwar and
Hrishikesh Jayakumar and
Vijay Raghunathan and
Kaushik Roy},
title = {Designing Energy-Efficient Intermittently Powered Systems Using Spin-Hall-Effect-Based
Nonvolatile {SRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {294--307},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2767033},
doi = {10.1109/TVLSI.2017.2767033},
timestamp = {Mon, 19 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RahaJSJRR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RahaR18,
author = {Arnab Raha and
Vijay Raghunathan},
title = {Approximating Beyond the Processor: Exploring Full-System Energy-Accuracy
Tradeoffs in a Smart Camera System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2884--2897},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2864269},
doi = {10.1109/TVLSI.2018.2864269},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RahaR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RatkovicPSUCV18,
author = {Ivan Ratkovic and
Oscar Palomar and
Milan Stanic and
Osman Sabri Unsal and
Adri{\'{a}}n Cristal and
Mateo Valero},
title = {Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power
Fused Multiply-Add},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {4},
pages = {639--652},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2784807},
doi = {10.1109/TVLSI.2017.2784807},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RatkovicPSUCV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RefanAN18,
author = {Fatemeh Refan and
Bijan Alizadeh and
Zainalabedin Navabi},
title = {Scalable Symbolic Simulation-Based Automatic Correction of Modern
Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {1845--1853},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2835833},
doi = {10.1109/TVLSI.2018.2835833},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RefanAN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RoelkeS18,
author = {Alec Roelke and
Mircea R. Stan},
title = {Controlling the Reliability of {SRAM} PUFs With Directed {NBTI} Aging
and Recovery},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2016--2026},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2836154},
doi = {10.1109/TVLSI.2018.2836154},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RoelkeS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RozoLZYG18,
author = {Laura Rozo and
Aaron Myles Landwehr and
Yan Zheng and
Chengmo Yang and
Guang Gao},
title = {Reliability-Aware Runtime Adaption Through a Statically Generated
Task Schedule},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {11--22},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2753242},
doi = {10.1109/TVLSI.2017.2753242},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RozoLZYG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RupeshBPMB18,
author = {Yomi Karthik Rupesh and
Payman Behnam and
Goverdhan Reddy Pandla and
Manikanth Miryala and
Mahdi Nazm Bojnordi},
title = {Accelerating k-Medians Clustering Using a Novel 4T-4R {RRAM} Cell},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2709--2722},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2808468},
doi = {10.1109/TVLSI.2018.2808468},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RupeshBPMB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SafarpourICSS18,
author = {Mehdi Safarpour and
Reza Inanlou and
Mostafa Charmi and
Omid Shoaei and
Olli Silv{\'{e}}n},
title = {ADC-Assisted Random Sampler Architecture for Efficient Sparse Signal
Acquisition},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1590--1594},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2821696},
doi = {10.1109/TVLSI.2018.2821696},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SafarpourICSS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SandhuE18,
author = {Tejinder Singh Sandhu and
Kamal El{-}Sankary},
title = {Beyond Rail-to-Rail Compliant Current Sources for Mismatch-Insensitive
Voltage-to-Time Conversion},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2165--2169},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2844728},
doi = {10.1109/TVLSI.2018.2844728},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SandhuE18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SannenaD18,
author = {Govinda Sannena and
Bishnu Prasad Das},
title = {Low Overhead Warning Flip-Flop Based on Charge Sharing for Timing
Slack Monitoring},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1223--1232},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2810954},
doi = {10.1109/TVLSI.2018.2810954},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SannenaD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SarmaTS18,
author = {Vineeth Sarma and
Rahul Thottathil and
Bibhudatta Sahoo},
title = {A DC-to-1-GHz Continuously Tunable Bandpass {ADC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {558--571},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2773468},
doi = {10.1109/TVLSI.2017.2773468},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SarmaTS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SawigunT18,
author = {Chutham Sawigun and
Surachoke Thanapitak},
title = {A 0.9-nW, 101-Hz, and 46.3-{\(\mathrm{\mu}\)}V\({}_{\mbox{rms}}\)
{IRN} Low-Pass Filter for {ECG} Acquisition Using {FVF} Biquads},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2290--2298},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2863706},
doi = {10.1109/TVLSI.2018.2863706},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SawigunT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SchulzeBSKK18,
author = {Travis E. Schulze and
Daryl G. Beetner and
Yiyu Shi and
Kevin A. Kwiat and
Charles A. Kamhoua},
title = {Combating Data Leakage Trojans in Commercial and {ASIC} Applications
With Time-Division Multiplexing and Random Encoding},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2007--2015},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2844180},
doi = {10.1109/TVLSI.2018.2844180},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SchulzeBSKK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SeoR18,
author = {Yeongkyo Seo and
Kaushik Roy},
title = {High-Density {SOT-MRAM} Based on Shared Bitline Structure},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1600--1603},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2822841},
doi = {10.1109/TVLSI.2018.2822841},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SeoR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShahTHN18,
author = {Sahil Shah and
Hakan Toreyin and
Jennifer Hasler and
Aishwarya Natarajan},
title = {Temperature Sensitivity and Compensation on a Reconfigurable Platform},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {604--607},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2773399},
doi = {10.1109/TVLSI.2017.2773399},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ShahTHN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShamsadiniFMM18,
author = {Shila Shamsadini and
Igor M. Filanovsky and
Pedram Mousavi and
Kambiz Moez},
title = {A 60-GHz Transmission Line Phase Shifter Using Varactors and Tunable
Inductors in 65-nm {CMOS} Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2073--2084},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2839709},
doi = {10.1109/TVLSI.2018.2839709},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShamsadiniFMM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShamsiMS18,
author = {Jafar Shamsi and
Karim Mohammadi and
Shahriar B. Shokouhi},
title = {A Hardware Architecture for Columnar-Organized Memory Based on {CMOS}
Neuron and Memristor Crossbar Arrays},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2795--2805},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2815025},
doi = {10.1109/TVLSI.2018.2815025},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShamsiMS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShangDWH18,
author = {Liuting Shang and
Shukai Duan and
Lidan Wang and
Tingwen Huang},
title = {{SRMC:} {A} Multibit Memristor Crossbar for Self-Renewing Image Mask},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2830--2841},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2844463},
doi = {10.1109/TVLSI.2018.2844463},
timestamp = {Sat, 19 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ShangDWH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShaoL18,
author = {Cuiping Shao and
Huiyun Li},
title = {Identifying Single-Event Transient Location Based on Compressed Sensing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {4},
pages = {768--777},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2778750},
doi = {10.1109/TVLSI.2017.2778750},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShaoL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SharafinejadAN18,
author = {Reza Sharafinejad and
Bijan Alizadeh and
Zainalabedin Navabi},
title = {Automatic Correction of Dynamic Power Management Architecture in Modern
Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {308--318},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2762006},
doi = {10.1109/TVLSI.2017.2762006},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SharafinejadAN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShenTLZL18,
author = {Haihua Shen and
Huazhe Tan and
Huawei Li and
Feng Zhang and
Xiaowei Li},
title = {LMDet: {A} "Naturalness" Statistical Method for Hardware Trojan Detection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {4},
pages = {720--732},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2781423},
doi = {10.1109/TVLSI.2017.2781423},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ShenTLZL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShinPM18,
author = {Donghwa Shin and
Massimo Poncino and
Enrico Macii},
title = {Thermal Management of Batteries Using Supercapacitor Hybrid Architecture
With Idle Period Insertion Strategy},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1159--1170},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2818758},
doi = {10.1109/TVLSI.2018.2818758},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShinPM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShreejithMVF18,
author = {Shanker Shreejith and
Libin K. Mathew and
A. Prasad Vinod and
Suhaib A. Fahmy},
title = {Efficient Spectrum Sensing for Aeronautical {LDACS} Using Low-Power
Correlators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1183--1191},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2806624},
doi = {10.1109/TVLSI.2018.2806624},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShreejithMVF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SongCZGUM18,
author = {Yan Song and
Chi{-}Hang Chan and
Yan Zhu and
Li Geng and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Passive Noise Shaping in {SAR} {ADC} With Improved Efficiency},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {416--420},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2764742},
doi = {10.1109/TVLSI.2017.2764742},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SongCZGUM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SrinivasaLCSGN18,
author = {Srivatsa Rangachar Srinivasa and
Xueqing Li and
Meng{-}Fan Chang and
John Sampson and
Sumeet Kumar Gupta and
Vijaykrishnan Narayanan},
title = {Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access
Capability Using Sequential Monolithic 3-D Integration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {4},
pages = {671--683},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2787562},
doi = {10.1109/TVLSI.2017.2787562},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SrinivasaLCSGN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TangV18,
author = {Yinqi Tang and
Naveen Verma},
title = {Energy-Efficient Pedestrian Detection System: Exploiting Statistical
Error Compensation for Lossy Memory Data Compression},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1301--1311},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2808104},
doi = {10.1109/TVLSI.2018.2808104},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TangV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TaoH18,
author = {Yonghong Tao and
Andreas Hierlemann},
title = {A 15-Channel 30-V Neural Stimulator for Spinal Cord Repair},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2185--2189},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2832051},
doi = {10.1109/TVLSI.2018.2832051},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TaoH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TavakkoliT18,
author = {Aryan Tavakkoli and
David B. Thomas},
title = {A High-Level Design Framework for the Automatic Generation of High-Throughput
Systolic Binomial-Tree Solvers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {341--354},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2761554},
doi = {10.1109/TVLSI.2017.2761554},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TavakkoliT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TavanaHPSH18,
author = {Mohammad Khavari Tavana and
Mohammad Hossein Hajkazemi and
Divya Pathak and
Ioannis Savidis and
Houman Homayoun},
title = {ElasticCore: {A} Dynamic Heterogeneous Platform With Joint Core and
Voltage/Frequency Scaling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {249--261},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2759219},
doi = {10.1109/TVLSI.2017.2759219},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TavanaHPSH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TehranipoorWKYC18,
author = {Fatemeh Tehranipoor and
Paul A. Wortman and
Nima Karimian and
Wei Yan and
John A. Chandy},
title = {{DVFT:} {A} Lightweight Solution for Power-Supply Noise-Based {TRNG}
Using Dynamic Voltage Feedback Tuning System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1084--1097},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2804258},
doi = {10.1109/TVLSI.2018.2804258},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TehranipoorWKYC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TeimooriAAA18,
author = {Mehri Teimoori and
Amirali Amirsoleimani and
Arash Ahmadi and
Majid Ahmadi},
title = {A 2M1M Crossbar Architecture: Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2608--2618},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2799951},
doi = {10.1109/TVLSI.2018.2799951},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TeimooriAAA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ThakkarTA18,
author = {Arpan Thakkar and
Srinivas Theertham and
Sankaran Aniruddhan},
title = {Phase Noise Analysis of Bipolar Class-C VCOs With Delay in Oscillator
Loop},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2873--2883},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2861818},
doi = {10.1109/TVLSI.2018.2861818},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ThakkarTA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ThibeaultG18,
author = {Claude Thibeault and
Ghyslain Gagnon},
title = {On the Analysis and the Mitigation of Power Supply Noise and Power
Distribution Network Impedance Variation for Scan-Based Delay Testing
Techniques},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1377--1390},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2817177},
doi = {10.1109/TVLSI.2018.2817177},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ThibeaultG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ToanTL18,
author = {Nguyen Van Toan and
Dam Minh Tung and
Jeong{-}Gun Lee},
title = {Analysis of Clock Scheduling in Frequency Domain for Digital Switching
Noise Suppressions},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1685--1698},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2830810},
doi = {10.1109/TVLSI.2018.2830810},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ToanTL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TorabiZ18,
author = {Mohammad Torabi and
Lihong Zhang},
title = {Electromigration- and Parasitic-Aware ILP-Based Analog Router},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {1854--1867},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2839698},
doi = {10.1109/TVLSI.2018.2839698},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TorabiZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TorunSDB18,
author = {Hakki Mert Torun and
Madhavan Swaminathan and
Anto Kavungal Davis and
Mohamed Lamine Faycal Bellaredj},
title = {A Global Bayesian Optimization Algorithm and Its Application to Integrated
System Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {4},
pages = {792--802},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2784783},
doi = {10.1109/TVLSI.2017.2784783},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TorunSDB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TripathiAM18,
author = {Jai Narayan Tripathi and
Ramachandra Achar and
Rakesh Malik},
title = {Fast Analysis of Time Interval Error in Current-Mode Drivers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {367--377},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2760010},
doi = {10.1109/TVLSI.2017.2760010},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TripathiAM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TsaiC18,
author = {Tsung{-}Han Tsai and
Shih{-}Wei Chen},
title = {Single-Chip Design for Intelligent Surveillance System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1637--1646},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2827385},
doi = {10.1109/TVLSI.2018.2827385},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TsaiC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TsaiHTCL18,
author = {Yu{-}Kai Tsai and
Yi{-}Keng Hsieh and
Hung{-}Yu Tsai and
Huan{-}Sheng Chen and
Liang{-}Hung Lu},
title = {A Concurrent Dual-Band and Dual-Mode Frequency Synthesizer for Radar
Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {945--957},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2799225},
doi = {10.1109/TVLSI.2018.2799225},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TsaiHTCL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TsaoCK18,
author = {Che{-}Wei Tsao and
Yuan{-}Hao Chang and
Tei{-}Wei Kuo},
title = {Boosting {NVDIMM} Performance With a Lightweight Caching Algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1518--1530},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2819210},
doi = {10.1109/TVLSI.2018.2819210},
timestamp = {Tue, 05 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TsaoCK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TsatsaragkosP18,
author = {Ioannis Tsatsaragkos and
Vassilis Paliouras},
title = {A Reconfigurable {LDPC} Decoder Optimized for 802.11n/ac Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {182--195},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2752086},
doi = {10.1109/TVLSI.2017.2752086},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TsatsaragkosP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VenkatachalamK18,
author = {Suganthi Venkatachalam and
Seok{-}Bum Ko},
title = {Approximate Sum-of-Products Designs Based on Distributed Arithmetic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1604--1608},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2818980},
doi = {10.1109/TVLSI.2018.2818980},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/VenkatachalamK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangCHLR18,
author = {Yujie Wang and
Pu Chen and
Jiang Hu and
Guofeng Li and
Jeyavijayan Rajendran},
title = {The Cat and Mouse in Split Manufacturing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {805--817},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2017.2787754},
doi = {10.1109/TVLSI.2017.2787754},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangCHLR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangCNYC18,
author = {Tian Wang and
Xiaoxin Cui and
Yewen Ni and
Dunshan Yu and
Xiaole Cui},
title = {Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power
FinFET Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {1922--1929},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2842067},
doi = {10.1109/TVLSI.2018.2842067},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangCNYC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangKSTT18,
author = {Shengcheng Wang and
Taeyoung Kim and
Zeyu Sun and
Sheldon X.{-}D. Tan and
Mehdi Baradaran Tahoori},
title = {Recovery-Aware Proactive {TSV} Repair for Electromigration Lifetime
Enhancement in 3-D ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {531--543},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2775586},
doi = {10.1109/TVLSI.2017.2775586},
timestamp = {Fri, 19 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangKSTT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangLW18,
author = {Yizhi Wang and
Jun Lin and
Zhongfeng Wang},
title = {An Energy-Efficient Architecture for Binary Weight Convolutional Neural
Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {280--293},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2767624},
doi = {10.1109/TVLSI.2017.2767624},
timestamp = {Fri, 21 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangLWCW18,
author = {Hsin{-}Pei Wang and
Chia{-}Chun Lin and
Chia{-}Cheng Wu and
Yung{-}Chih Chen and
Chun{-}Yao Wang},
title = {On Synthesizing Memristor-Based Logic Circuits With Minimal Operational
Pulses},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2842--2852},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2816023},
doi = {10.1109/TVLSI.2018.2816023},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangLWCW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangLZ18,
author = {Xiaoping Wang and
Shuai Li and
Zhigang Zeng},
title = {Configurable Logic Operations Using Hybrid {CRS-CMOS} Cells},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2641--2647},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2791625},
doi = {10.1109/TVLSI.2018.2791625},
timestamp = {Sun, 21 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangLZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangP18,
author = {Xing Wang and
Derek Chi{-}Wai Pao},
title = {Memory-Based Architecture for Multicharacter Aho-Corasick String Matching},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {143--154},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2753843},
doi = {10.1109/TVLSI.2017.2753843},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangWFCL18,
author = {Lei Wang and
Chundong Wu and
Lisong Feng and
Alan Chang and
Yong Lian},
title = {A Low-Power Forward and Reverse Body Bias Generator in {CMOS} 40 nm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1403--1407},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2810108},
doi = {10.1109/TVLSI.2018.2810108},
timestamp = {Thu, 21 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangWFCL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangZCUM18,
author = {Guan{-}Cheng Wang and
Yan Zhu and
Chi{-}Hang Chan and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Gain Error Calibrations for Two-Step ADCs: Optimizations Either in
Accuracy or Chip Area},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2279--2289},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2865595},
doi = {10.1109/TVLSI.2018.2865595},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangZCUM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangZTLL18,
author = {Lidan Wang and
Chenchang Zhan and
Junyao Tang and
Yang Liu and
Guofeng Li},
title = {A 0.9-V 33.7-ppm/{\textdegree}C 85-nW Sub-Bandgap Voltage Reference
Consisting of Subthreshold MOSFETs and Single {BJT}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2190--2194},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2836331},
doi = {10.1109/TVLSI.2018.2836331},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangZTLL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WeinerMRS18,
author = {Michael Weiner and
Salvador Manich and
Rosa Rodr{\'{\i}}guez{-}Monta{\~{n}}{\'{e}}s and
Georg Sigl},
title = {The Low Area Probing Detector as a Countermeasure Against Invasive
Attacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {392--403},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2762630},
doi = {10.1109/TVLSI.2017.2762630},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WeinerMRS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuLLR18,
author = {Cheng{-}Hung Wu and
Sheng{-}Lin Lin and
Kuen{-}Jong Lee and
Sudhakar M. Reddy},
title = {A Repair-for-Diagnosis Methodology for Logic Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2254--2267},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2856527},
doi = {10.1109/TVLSI.2018.2856527},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WuLLR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuTS18,
author = {Chung{-}Shiang Wu and
Makoto Takamiya and
Takayasu Sakurai},
title = {Clocked Hysteresis Control Scheme With Power-Law Frequency Scaling
in Buck Converter to Improve Light-Load Efficiency for IoT Sensor
Nodes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1139--1150},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2806928},
doi = {10.1109/TVLSI.2018.2806928},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WuTS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XieLGHX18,
author = {Mimi Xie and
Shuangchen Li and
Alvin Oliver Glova and
Jingtong Hu and
Yuan Xie},
title = {Securing Emerging Nonvolatile Main Memory With Fast and Energy-Efficient
{AES} In-Memory Implementation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2443--2455},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2865133},
doi = {10.1109/TVLSI.2018.2865133},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XieLGHX18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuKFTH18,
author = {Xiaolin Xu and
Shahrzad Keshavarz and
Domenic Forte and
Mark M. Tehranipoor and
Daniel E. Holcomb},
title = {Bimodal Oscillation as a Mechanism for Autonomous Majority Voting
in PUFs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2431--2442},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2861328},
doi = {10.1109/TVLSI.2018.2861328},
timestamp = {Tue, 30 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XuKFTH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuSH18,
author = {Wenbin Xu and
Sachin S. Sapatnekar and
Jiang Hu},
title = {A Simple Yet Efficient Accuracy-Configurable Adder Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1112--1125},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2803081},
doi = {10.1109/TVLSI.2018.2803081},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XuSH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XueWZCWPKKX18,
author = {Linuo Xue and
Bi Wu and
Beibei Zhang and
Yuanqing Cheng and
Peiyuan Wang and
Chando Park and
Jimmy J. Kan and
Seung H. Kang and
Yuan Xie},
title = {An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {484--495},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2780522},
doi = {10.1109/TVLSI.2017.2780522},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XueWZCWPKKX18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YabuuchiTFTSN18,
author = {Makoto Yabuuchi and
Yasumasa Tsukamoto and
Hidehiro Fujiwara and
Miki Tanaka and
Shinji Tanaka and
Koji Nii},
title = {A 28-nm 1R1W Two-Port 8T {SRAM} Macro With Screening Circuitry Against
Read Disturbance and Wordline Coupling Noise Failures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2335--2344},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2864267},
doi = {10.1109/TVLSI.2018.2864267},
timestamp = {Mon, 24 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YabuuchiTFTSN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangDV18,
author = {Jinghua Yang and
Aykut Dengi and
Sarma B. K. Vrudhula},
title = {Design Considerations for Energy-Efficient and Variation-Tolerant
Nonvolatile Logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2628--2640},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2812700},
doi = {10.1109/TVLSI.2018.2812700},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangDV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangKLKS18,
author = {Teng Yang and
Doyun Kim and
Jiangyi Li and
Peter R. Kinget and
Mingoo Seok},
title = {\emph{In{\textasciitilde}Situ} and In-Field Technique for Monitoring
and Decelerating {NBTI} in 6T-SRAM Register Files},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2241--2253},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2856528},
doi = {10.1109/TVLSI.2018.2856528},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangKLKS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangLZM18,
author = {Kexin Yang and
Taizhi Liu and
Rui Zhang and
Linda Milor},
title = {A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator
for Both Traditional {CMOS} and FinFET Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2470--2482},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2861769},
doi = {10.1109/TVLSI.2018.2861769},
timestamp = {Wed, 01 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YangLZM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangM18,
author = {Ping{-}Lin Yang and
Malgorzata Marek{-}Sadowska},
title = {High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1209--1222},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2814627},
doi = {10.1109/TVLSI.2018.2814627},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YantirEK18,
author = {Hasan Erdem Yantir and
Ahmed M. Eltawil and
Fadi J. Kurdahi},
title = {A Two-Dimensional Associative Processor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1659--1670},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2827262},
doi = {10.1109/TVLSI.2018.2827262},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YantirEK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YeS18,
author = {Jheng{-}Hao Ye and
Ming{-}Der Shieh},
title = {Low-Complexity {VLSI} Design of Large Integer Multipliers for Fully
Homomorphic Encryption},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1727--1736},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2829539},
doi = {10.1109/TVLSI.2018.2829539},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YeS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YinLXLW18,
author = {Shouyi Yin and
Tianyi Lu and
Zhicong Xie and
Leibo Liu and
Shaojun Wei},
title = {Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data
Access for {MLC} {STT-RAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2345--2357},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2862388},
doi = {10.1109/TVLSI.2018.2862388},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YinLXLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YinSVETH18,
author = {Xunzhao Yin and
Behnam Sedighi and
Melinda Varga and
M{\'{a}}ria Ercsey{-}Ravasz and
Zolt{\'{a}}n Toroczkai and
Xiaobo Sharon Hu},
title = {Efficient Analog Circuits for Boolean Satisfiability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {155--167},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2754192},
doi = {10.1109/TVLSI.2017.2754192},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YinSVETH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YingBL18,
author = {Yutong Ying and
Xuefei Bai and
Fujiang Lin},
title = {A 1-Gb/s 6-10-GHz, Filterless, Pulsed {UWB} Transmitter With Symmetrical
Waveform Analysis and Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1171--1182},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2808417},
doi = {10.1109/TVLSI.2018.2808417},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YingBL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YuLLWTS18,
author = {Hsueh{-}Ling Yu and
Yih{-}Lang Li and
Tzu{-}Yi Liao and
Tianchen Wang and
Shu{-}Fei Tsai and
Yiyu Shi},
title = {Fast and Accurate Emissivity and Absolute Temperature Maps Measurement
for Integrated Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {912--923},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2017.2788437},
doi = {10.1109/TVLSI.2017.2788437},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YuLLWTS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZandevakiliM18,
author = {Hamed Zandevakili and
Ali Mahani},
title = {A New {ASIC} Structure With Self-Repair Capability Using Field-Programmable
Nanowire Interconnect Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2268--2278},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2856083},
doi = {10.1109/TVLSI.2018.2856083},
timestamp = {Tue, 20 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZandevakiliM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZervakisNXSP18,
author = {Georgios Zervakis and
Fotios Ntouskas and
Sotirios Xydis and
Dimitrios Soudris and
Kiamal Z. Pekmestzi},
title = {VOSsim: {A} Framework for Enabling Fast Voltage Overscaling Simulation
for Approximate Computing Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1204--1208},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2803202},
doi = {10.1109/TVLSI.2018.2803202},
timestamp = {Wed, 06 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZervakisNXSP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhanRLS18,
author = {Xin Zhan and
Joseph Riad and
Peng Li and
Edgar S{\'{a}}nchez{-}Sinencio},
title = {Design Space Exploration of Distributed On-Chip Voltage Regulation
Under Stability Constraint},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {8},
pages = {1580--1584},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2818079},
doi = {10.1109/TVLSI.2018.2818079},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhanRLS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangKFMJ18,
author = {Jiangwei Zhang and
Donald Kline Jr. and
Liang Fang and
Rami G. Melhem and
Alex K. Jones},
title = {Data Block Partitioning Methods to Mitigate Stuck-At Faults in Limited
Endurance Memories},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2358--2371},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2858186},
doi = {10.1109/TVLSI.2018.2858186},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangKFMJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangLLYZZPZ18,
author = {Ye Zhang and
Wenlong Lyu and
Wai{-}Shing Luk and
Fan Yang and
Hai Zhou and
Dian Zhou and
David Z. Pan and
Xuan Zeng},
title = {Cut Redistribution and Insertion for Advanced 1-D Layout Design via
Network Flow Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1613--1626},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2828603},
doi = {10.1109/TVLSI.2018.2828603},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangLLYZZPZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangSZZC18,
author = {Hong Zhang and
Junqiang Sun and
Jie Zhang and
Ruizhi Zhang and
Anthony Chan Carusone},
title = {A Low-Power Pipelined-SAR {ADC} Using Boosted Bucket-Brigade Device
for Residue Charge Processing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1763--1776},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2832472},
doi = {10.1109/TVLSI.2018.2832472},
timestamp = {Mon, 23 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangSZZC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangWRT18,
author = {Dongrong Zhang and
Xiaoxiao Wang and
Md. Tauhidur Rahman and
Mark M. Tehranipoor},
title = {An On-Chip Dynamically Obfuscated Wrapper for Protecting Supply Chain
Against {IP} and {IC} Piracies},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2456--2469},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2850807},
doi = {10.1109/TVLSI.2018.2850807},
timestamp = {Wed, 15 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangWRT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhaoT18,
author = {Hengyang Zhao and
Sheldon X.{-}D. Tan},
title = {Postvoiding {FEM} Analysis for Electromigration Failure Characterization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2483--2493},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2861358},
doi = {10.1109/TVLSI.2018.2861358},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhaoT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhouZCPZZ18,
author = {Hao Zhou and
Hengliang Zhu and
Tao Cui and
David Z. Pan and
Dian Zhou and
Xuan Zeng},
title = {Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With
a Novel Adaptive Strategy Finite Element Method},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1312--1325},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2811417},
doi = {10.1109/TVLSI.2018.2811417},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhouZCPZZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhuS18,
author = {Kehan Zhu and
Vishal Saxena},
title = {From Design to Test: {A} High-Speed {PRBS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2099--2107},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2834373},
doi = {10.1109/TVLSI.2018.2834373},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhuS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhuZWC018,
author = {Maohua Zhu and
Youwei Zhuo and
Chao Wang and
Wenguang Chen and
Yuan Xie},
title = {Performance Evaluation and Optimization of HBM-Enabled {GPU} for Data-Intensive
Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {831--840},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2791442},
doi = {10.1109/TVLSI.2018.2791442},
timestamp = {Thu, 25 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhuZWC018.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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