"OASIS: A 28-nm 32-kb SRAM-Based Computing-in-Memory Design With Output ..."

Qingyu Guo et al. (2024)

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DOI: 10.1109/TCSII.2023.3339622

access: closed

type: Journal Article

metadata version: 2024-04-15

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Qingyu Guo, Nanbing Pan, Xin Qiao, Xiaoxin Cui, Yuan Wang:
OASIS: A 28-nm 32-kb SRAM-Based Computing-in-Memory Design With Output Activation Sparsity Support. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1899-1903 (2024)

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