Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic ..."

Haonan Zhu et al. (2024)

> Home

Details and statistics

DOI: 10.1109/TCSI.2024.3395442

access: closed

type: Journal Article

metadata version: 2024-07-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcasI/ZhuWYCYL24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcasI/ZhuWYCYL24
Haonan Zhu, Bi Wu, Tianyang Yu, Ke Chen, Chenggang Yan, Weiqiang Liu:
A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 71(7): 3165-3178 (2024)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.