"Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed ..."

Jin-Tai Yan (2019)

> Home

Details and statistics

DOI: 10.1109/TCAD.2018.2818728

access: closed

type: Journal Article

metadata version: 2020-09-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcad/Yan19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcad/Yan19
Jin-Tai Yan:
Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed PCB Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(3): 512-525 (2019)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.