"Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance ..."

Lomash Chandra Acharya et al. (2023)

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DOI: 10.1109/TCAD.2022.3231173

access: closed

type: Journal Article

metadata version: 2023-08-05

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Lomash Chandra Acharya, Arvind Kumar Sharma, Neeraj Mishra, Khoirom Johnson Singh, Mahipal Dargupally, Nayakanti Sai Shabarish, Ajoy Mandal, Venkatraman Ramakrishnan, Sudeb Dasgupta, Anand Bulusu:
Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2657-2663 (2023)

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