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"C1C: A configurable, compiler-guided STT-RAM L1 cache."

Yong Li et al. (2013)

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DOI: 10.1145/2541228.2555308

access: open

type: Journal Article

metadata version: 2023-10-22

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Yong Li, Yaojun Zhang, Hai Li, Yiran Chen, Alex K. Jones:
C1C: A configurable, compiler-guided STT-RAM L1 cache. ACM Trans. Archit. Code Optim. 10(4): 52:1-52:22 (2013)

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