"A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and ..."

Yuji Yokoyama et al. (2001)

> Home

Details and statistics

DOI: 10.1109/4.910489

access: closed

type: Journal Article

metadata version: 2022-04-04

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/YokoyamaIHKAKUT01
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/YokoyamaIHKAKUT01
Yuji Yokoyama, Nobutaka Itoh, Masatoshi Hasegawa, Masahiro Katayama, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, Eiji Yamasaki, Masaya Todokoro, Keinosuke Toriyama, Hiroshi Miki, Masayoshi Yagyu, Kazumasa Takashima, Toru Kobayashi, Syuichi Miyaoka, Nobuo Tamba:
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%. IEEE J. Solid State Circuits 36(3): 503-509 (2001)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.