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"A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and ..."

Yuji Yokoyama et al. (2001)

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DOI: 10.1109/4.910489

access: closed

type: Journal Article

metadata version: 2022-04-04

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Yuji Yokoyama, Nobutaka Itoh, Masatoshi Hasegawa, Masahiro Katayama, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, Eiji Yamasaki, Masaya Todokoro, Keinosuke Toriyama, Hiroshi Miki, Masayoshi Yagyu, Kazumasa Takashima, Toru Kobayashi, Syuichi Miyaoka, Nobuo Tamba:
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%. IEEE J. Solid State Circuits 36(3): 503-509 (2001)

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