"A cell transistor scalable DRAM array architecture."

Daisaburo Takashima, Hiroaki Nakano (2002)

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DOI: 10.1109/4.997851

access: closed

type: Journal Article

metadata version: 2022-04-04

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Daisaburo Takashima, Hiroaki Nakano:
A cell transistor scalable DRAM array architecture. IEEE J. Solid State Circuits 37(5): 587-591 (2002)

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