Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A cell transistor scalable DRAM array architecture."

Daisaburo Takashima, Hiroaki Nakano (2002)

> Home

Details and statistics

DOI: 10.1109/4.997851

access: closed

type: Journal Article

metadata version: 2022-04-04

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/TakashimaN02
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/TakashimaN02
Daisaburo Takashima, Hiroaki Nakano:
A cell transistor scalable DRAM array architecture. IEEE J. Solid State Circuits 37(5): 587-591 (2002)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.