Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture."

Yasuhiro Takai et al. (1994)

> Home

Details and statistics

DOI: 10.1109/4.280691

access: closed

type: Journal Article

metadata version: 2023-05-03

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/TakaiNKKYKOFW94
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/TakaiNKKYKOFW94
Yasuhiro Takai, Mamoru Nagase, Mamoru Kitamura, Yasuji Koshikawa, Naoyuki Yoshida, Yasuaki Kobayashi, Takashi Obara, Yukio Fukuzo, Hiroshi Watanabe:
250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture. IEEE J. Solid State Circuits 29(4): 426-431 (1994)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.