"A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology."

Daniel L. Stasiak, Farnaz Mounes-Toussi, Salvatore N. Storino (2001)

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DOI: 10.1109/4.953483

access: closed

type: Journal Article

metadata version: 2022-04-06

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Daniel L. Stasiak, Farnaz Mounes-Toussi, Salvatore N. Storino:
A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology. IEEE J. Solid State Circuits 36(10): 1546-1552 (2001)

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