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"A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and ..."

Kyomin Sohn et al. (2013)

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DOI: 10.1109/JSSC.2012.2213512

access: closed

type: Journal Article

metadata version: 2020-08-30

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  - journals/jssc/SohnNSSBKLJHJLPLLJPPCKCCJKCJKLC13
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  - https://dblp.org/rec/journals/jssc/SohnNSSBKLJHJLPLLJPPCKCCJKCJKLC13
Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Seok-Hun Hyun, Hanki Jeoung, Ki Won Lee, Jun-Seok Park, Jongeun Lee, Byunghyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Byungchul Kim, Jung-Hwan Choi, Seong-Jin Jang, Chi-Wook Kim, Jung-Bae Lee, Joo-Sun Choi:
A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme. IEEE J. Solid State Circuits 48(1): 168-177 (2013)

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