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Yong Shim
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2020 – today
- 2024
- [j11]Keun-Yong Chung, Honggu Kim, Yerim An, Kiho Seong, Dong-Hyun Shin, Kwang-Hyun Baek, Yong Shim:
8T-SRAM Based Process-In-Memory (PIM) System With Current Mirror for Accurate MAC Operation. IEEE Access 12: 24254-24261 (2024) - [c7]Honggu Kim, Yerim An, Yong Shim:
Coupled 7T 1C SRAM based in-memory computing architecture with gain/offset error auto-compensated SAR ADC. ISLPED 2024: 1-6 - 2022
- [j10]Van-Thai Dang, Myeong-Gyu Yang, Chung-Hee Jang, Sukho Lee, Yong Shim, Kwang-Hyun Baek:
A Highly Efficient Time-Based MPPT Circuit With Extended Power Range and Minimized Tuning Switching Frequency. IEEE Access 10: 64004-64017 (2022) - [j9]Dong-Kyu Jung, Kiho Seong, Jae-Soub Han, Yong Shim, Kwang-Hyun Baek:
A 0.5 V 10 b 3 MS/s 2-Then-1b/Cycle SAR ADC With Digital-Based Time-Domain Reference and Dual-Mode Comparator. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 909-913 (2022) - [j8]Kiho Seong, Jae-Soub Han, Yong Shim, Kwang-Hyun Baek:
A 2.5 GS/s 7-Bit 5-Way Time-Interleaved SAR ADC With On-Chip Background Offset and Timing-Skew Calibration. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 4043-4047 (2022) - 2021
- [j7]Van-Thai Dang, Myeong-Gyu Yang, Yong Shim, Woojoo Lee, Kwang-Hyun Baek:
An Accurate Time-Based MPPT Circuit With Two-Period Tracking Algorithm and Convergence Range Averaging Technique for IoT Applications. IEEE Access 9: 31401-31410 (2021) - [j6]Jae-Soub Han, Tae-Hyeok Eom, Seong-Wook Choi, Kiho Seong, Dong-Hyun Yoon, Tony Tae-Hyoung Kim, Kwang-Hyun Baek, Yong Shim:
A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator. Sensors 21(20): 6824 (2021) - 2020
- [j5]Minsuk Koo, Gopalakrishnan Srinivasan, Yong Shim, Kaushik Roy:
sBSNN: Stochastic-Bits Enabled Binary Spiking Neural Network With On-Chip Learning for Energy Efficient Neuromorphic Computing at the Edge. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(8): 2546-2555 (2020) - [j4]Amogh Agrawal, Indranil Chakraborty, Deboleena Roy, Utkarsh Saxena, Saima Sharmin, Minsuk Koo, Yong Shim, Gopalakrishnan Srinivasan, Chamika M. Liyanagedera, Abhronil Sengupta, Kaushik Roy:
Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2481-2494 (2020) - [i5]Minsuk Koo, Gopalakrishnan Srinivasan, Yong Shim, Kaushik Roy:
sBSNN: Stochastic-Bits Enabled Binary Spiking Neural Network with On-Chip Learning for Energy Efficient Neuromorphic Computing at the Edge. CoRR abs/2002.11163 (2020)
2010 – 2019
- 2018
- [b1]Yong Shim:
Stochastic Algorithms for Optimization: Devices, Circuits, and Architecture. Purdue University, USA, 2018 - 2017
- [j3]Karthik Yogendra, Chamika M. Liyanagedera, Deliang Fan, Yong Shim, Kaushik Roy:
Coupled Spin-Torque Nano-Oscillator-Based Computation: A Simulation Study. ACM J. Emerg. Technol. Comput. Syst. 13(4): 56:1-56:24 (2017) - [c6]Yong Shim, Akhilesh Jaiswal, Kaushik Roy:
Stochastic Switching of SHE-MTJ as a Natural Annealer for Efficient Combinatorial Optimization. ICCD 2017: 605-608 - [i4]Yong Shim, Shuhan Chen, Abhronil Sengupta, Kaushik Roy:
Stochastic Spin-Orbit Torque Devices as Elements for Bayesian Inference. CoRR abs/1707.04687 (2017) - 2016
- [j2]Abhronil Sengupta, Yong Shim, Kaushik Roy:
Proposal for an All-Spin Artificial Neural Network: Emulating Neural and Synaptic Functionalities Through Domain Wall Motion in Ferromagnets. IEEE Trans. Biomed. Circuits Syst. 10(6): 1152-1160 (2016) - [c5]Karthik Yogendra, Deliang Fan, Yong Shim, Minsuk Koo, Kaushik Roy:
Computing with coupled Spin Torque Nano Oscillators. ASP-DAC 2016: 312-317 - [c4]Yong Shim, Abhronil Sengupta, Kaushik Roy:
Low-power approximate convolution computing unit with domain-wall motion based "spin-memristor" for image processing applications. DAC 2016: 21:1-21:6 - [i3]Yong Shim, Akhilesh Jaiswal, Kaushik Roy:
Ising spin model using Spin-Hall Effect (SHE) induced magnetization reversal in Magnetic-Tunnel-Junction. CoRR abs/1609.05926 (2016) - 2015
- [i2]Abhronil Sengupta, Yong Shim, Kaushik Roy:
Simulation studies of an All-Spin Artificial Neural Network: Emulating neural and synaptic functionalities through domain wall motion in ferromagnets. CoRR abs/1510.00459 (2015) - 2014
- [i1]Deliang Fan, Yong Shim, Anand Raghunathan, Kaushik Roy:
STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks. CoRR abs/1412.8648 (2014) - 2013
- [j1]Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Seok-Hun Hyun, Hanki Jeoung, Ki Won Lee, Jun-Seok Park, Jongeun Lee, Byunghyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Byungchul Kim, Jung-Hwan Choi, Seong-Jin Jang, Chi-Wook Kim, Jung-Bae Lee, Joo-Sun Choi:
A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme. IEEE J. Solid State Circuits 48(1): 168-177 (2013) - 2012
- [c3]Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Hanki Jeoung, Ki Won Lee, Junsuk Park, Jongeun Lee, Byunghyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Jang Seok Choi, Byung-Sick Moon, Jung-Hwan Choi, Byungchul Kim, Seong-Jin Jang, Joo-Sun Choi, Kyungseok Oh:
A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme. ISSCC 2012: 38-40
2000 – 2009
- 2006
- [c2]Youngkwon Jo, Yong Shim, Soo Hwan Kim, Suki Kim, Kwanjun Cho:
A mixed-structure delay locked-loop with wide range and fast locking. ISCAS 2006 - [c1]Yong Shim, Youngkwon Jo, Soo Hwan Kim, Suki Kim, Kwanjun Cho:
A register controlled delay locked loop using a TDC and a new fine delay line scheme. ISCAS 2006
Coauthor Index
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last updated on 2024-10-23 21:21 CEST by the dblp team
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