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"A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL ..."

Kyeongho Lee, Joonhyung Kim, Jongsun Park (2024)

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DOI: 10.1109/JSSC.2023.3334566

access: closed

type: Journal Article

metadata version: 2024-06-18

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Kyeongho Lee, Joonhyung Kim, Jongsun Park:
A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharing-Based In-SRAM DAC/ADC Operations. IEEE J. Solid State Circuits 59(6): 1926-1937 (2024)

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