Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control."

Sang-Bo Lee et al. (2005)

> Home

Details and statistics

DOI: 10.1109/JSSC.2004.837983

access: closed

type: Journal Article

metadata version: 2022-03-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/LeeJKHJCL05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/LeeJKHJCL05
Sang-Bo Lee, Seong-Jin Jang, Jin-Seok Kwak, Sang-Jun Hwang, Young-Hyun Jun, Soo-In Cho, Chil-Gee Lee:
A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control. IEEE J. Solid State Circuits 40(1): 223-232 (2005)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.