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"A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and ..."

Jeongkyun Kim et al. (2024)

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DOI: 10.1109/JSSC.2024.3355948

access: closed

type: Journal Article

metadata version: 2024-04-15

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Jeongkyun Kim, Byungho Yook, Youngo Lee, Taemin Choi, Kyuwon Choi, Chanho Lee, Juchang Lee, Hyeongcheol Kim, Seok Yun, Changhoon Do, Minwoo Kwak, Mijoung Kim, Yunrong Li, Hoyoung Tang, Jaeyoung Kim, Inhak Lee, Dongwook Seo, Sangyeop Baeck:
A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology. IEEE J. Solid State Circuits 59(4): 1216-1224 (2024)

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