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ORCID"A monolithic 156 Mb/s clock and data recovery PLL circuit using the ..."
Noboru Ishihara, Yukio Akazawa (1994)
- Noboru Ishihara, Yukio Akazawa:
A monolithic 156 Mb/s clock and data recovery PLL circuit using the sample-and-hold technique. IEEE J. Solid State Circuits 29(12): 1566-1571 (1994)
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