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"CMOS implementation of a multiple-valued logic signed-digit full adder ..."
Alejandro F. González et al. (2001)
- Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder:
CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices. IEEE J. Solid State Circuits 36(6): 924-932 (2001)
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