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"1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed ..."

Hiroki Fujisawa et al. (2005)

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DOI: 10.1109/JSSC.2005.845555

access: closed

type: Journal Article

metadata version: 2022-03-02

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Hiroki Fujisawa, Masayuki Nakamura, Yasuhiro Takai, Yasuji Koshikawa, Tatsuya Matano, Seiji Narui, Narikazu Usuki, Chiaki Dono, Shinichi Miyatake, Makoto Morino, Koji Arai, Shuichi Kubouchi, Isamu Fujii, Hideyuki Yoko, Takao Adachi:
1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer. IEEE J. Solid State Circuits 40(4): 862-869 (2005)

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