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"A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme."
Go Matsukawa et al. (2015)
- Go Matsukawa, Yohei Nakata, Yasuo Sugure, Shigeru Oho, Yuta Kimi, Masafumi Shimozawa, Shuhei Yoshida, Hiroshi Kawaguchi
, Masahiko Yoshimoto:
A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme. IEICE Trans. Electron. 98-C(4): 333-339 (2015)
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