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"Energy-efficient system-on-chip reconfigurable architecture design for sum ..."

K. R. Sarath Chandran, Premanand Venkatesh Chandramani (2022)

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DOI: 10.1002/CPE.5461

access: closed

type: Journal Article

metadata version: 2022-04-01

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  - journals/concurrency/ChandranC22
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  - https://dblp.org/rec/journals/concurrency/ChandranC22
K. R. Sarath Chandran, Premanand Venkatesh Chandramani:
Energy-efficient system-on-chip reconfigurable architecture design for sum of absolute difference computation in motion estimation process of H.265/HEVC video encoding. Concurr. Comput. Pract. Exp. 34(8) (2022)

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