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"Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, ..."

Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula (2006)

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DOI: 10.1166/JOLPE.2006.065

access: closed

type: Journal Article

metadata version: 2020-05-22

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  - https://dblp.org/rec/journals/jolpe/BhardwajCV06
Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula:
Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. J. Low Power Electron. 2(2): 240-250 (2006)

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