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"Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD ..."

Guangyi Lu, Yuan Wang, Xing Zhang (2016)

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DOI: 10.1587/TRANSELE.E99.C.590

access: closed

type: Journal Article

metadata version: 2020-04-11

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  persistent URL:
  - https://dblp.org/rec/journals/ieicet/LuWZ16
Guangyi Lu, Yuan Wang, Xing Zhang:
Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process. IEICE Trans. Electron. 99-C(5): 590-596 (2016)

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