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"16-layer 3D Vertical RRAM with Low Read Latency (18ns), High Nonlinearity ..."

Yaxin Ding et al. (2023)

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DOI: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185341

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-12

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  dblp key:
  - conf/vlsit/DingYLGWJLCWWGX23
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  persistent URL:
  - https://dblp.org/rec/conf/vlsit/DingYLGWJLCWWGX23
Yaxin Ding, Jianguo Yang, Yu Liu, Jianfeng Gao, Yuan Wang, Pengfei Jiang, Shuxian Lv, Yuting Chen, Boping Wang, Wei Wei, Tiancheng Gong, Kanhao Xue, Qing Luo, Xiangshui Miao, Ming Liu:
16-layer 3D Vertical RRAM with Low Read Latency (18ns), High Nonlinearity (>5000) and Ultra-low Leakage Current (~pA) Self-Selective Cells. VLSI Technology and Circuits 2023: 1-2

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